Wiki source code of Intermediate Processors
Version 35.1 by cds on 2015/03/27 10:34
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| 1 | This section describes the intermediate processors that are available. For a description of what intermediate processors actually are, see [[doc:KLay Layered]]. | ||
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| 3 | Each intermediate processor is described by its required preconditions, its postconditions, the slot where it should be placed in and dependencies to intermediate processors in the same slot. The descriptions are kept very brief, since layout processors are usually well documented. Programmers using layout processors need not worry about dependencies. However, when adding a new processor, dependencies matter. For more information, see the documentation of IntermediateLayoutProcessor. | ||
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| 5 | The following table provides an overview of all available layout processors and the slots they can be placed in. Note that a processor may appear in more than one slot. Within each slot, processors are ordered by theirs dependencies on each other. | ||
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| 9 | |=((( | ||
| 10 | Slot | ||
| 11 | )))|=((( | ||
| 12 | Processor | ||
| 13 | )))|=(% colspan="1" %)(% colspan="1" %) | ||
| 14 | ((( | ||
| 15 | Tested | ||
| 16 | ))) | ||
| 17 | |((( | ||
| 18 | Before phase 1 | ||
| 19 | )))|((( | ||
| 20 | Graph Transformer | ||
| 21 | Comment Preprocessor | ||
| 22 | Edge And Layer Constraint Edge Reverser | ||
| 23 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 24 | ((( | ||
| 25 | |||
| 26 | \\ | ||
| 27 | ))) | ||
| 28 | |((( | ||
| 29 | Before phase 2 | ||
| 30 | )))|((( | ||
| 31 | Big Nodes Processor | ||
| 32 | Label Dummy Inserter | ||
| 33 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 34 | ((( | ||
| 35 | \\ | ||
| 36 | ))) | ||
| 37 | |((( | ||
| 38 | Before phase 3 | ||
| 39 | )))|((( | ||
| 40 | Layer Constraint Processor | ||
| 41 | Hierarchical Port Constraint Processor | ||
| 42 | Long Edge Splitter | ||
| 43 | Port Side Processor | ||
| 44 | Label Dummy Switcher | ||
| 45 | Inverted Port Processor | ||
| 46 | Self Loop Processor | ||
| 47 | Port List Sorter | ||
| 48 | North South Port Preprocessor | ||
| 49 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 50 | ((( | ||
| 51 | |||
| 52 | \\\\\\\\\\\\\\ | ||
| 53 | ))) | ||
| 54 | |((( | ||
| 55 | Before phase 4 | ||
| 56 | )))|((( | ||
| 57 | In Layer Constraint Processor | ||
| 58 | Hierarchical Port Dummy Size Processor | ||
| 59 | Hyperedge Dummy Merger | ||
| 60 | Label Side Selector | ||
| 61 | Label And Node Size Processor | ||
| 62 | Node Margin Calculator | ||
| 63 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 64 | ((( | ||
| 65 | |||
| 66 | \\\\\\\\\\\\ | ||
| 67 | ))) | ||
| 68 | |((( | ||
| 69 | Before phase 5 | ||
| 70 | )))|((( | ||
| 71 | Layer Size and Graph Height Calculator | ||
| 72 | Hierarchical Port Position Processor | ||
| 73 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 74 | ((( | ||
| 75 | \\ | ||
| 76 | ))) | ||
| 77 | |((( | ||
| 78 | After phase 5 | ||
| 79 | )))|((( | ||
| 80 | Comment Postprocessor | ||
| 81 | Hypernode Processor | ||
| 82 | Hierarchical Port Orthogonal Edge Router | ||
| 83 | Long Edge Joiner | ||
| 84 | North South Port Postprocessor | ||
| 85 | Label Dummy Remover | ||
| 86 | Reversed Edge Restorer | ||
| 87 | Graph Transformer | ||
| 88 | End Label Processor | ||
| 89 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 90 | ((( | ||
| 91 | |||
| 92 | \\\\\\\\\\\\\\ | ||
| 93 | ))) |