Wiki source code of Intermediate Processors
Last modified by Alexander Schulz-Rosengarten on 2023/07/11 10:33
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| 1 | This section lists the intermediate processors that are available. For a description of what intermediate processors actually are, see [[doc:KIELER.Discontinued Projects.Layout Algorithms (KLay).KLay Layered.WebHome]]. | ||
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| 3 | To add a new intermediate processor, create a corresponding class in the {{code language="none"}}...klay.layered.intermediate{{/code}} package and add proper documentation (refer to existing intermediate processors). Choose which intermediate processing slot(s) the processor can be run in. Then think about possible dependencies to other processors in that slot. Add the processor to the {{code language="none"}}IntermediateProcessingStrategy{{/code}} enumeration such, that all processors it depends on precede the definition of the new processor. | ||
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| 5 | The following table provides an overview of all available layout processors and the slots they can be placed in. Note that a processor may appear in more than one slot. Within each slot, processors are ordered by theirs dependencies on each other. For more documentation on how the processors actually work, refer to their Javadoc documentation. | ||
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| 7 | |=((( | ||
| 8 | Slot | ||
| 9 | )))|=((( | ||
| 10 | Processor | ||
| 11 | )))|=(% colspan="1" %)(% colspan="1" %) | ||
| 12 | ((( | ||
| 13 | Tested | ||
| 14 | ))) | ||
| 15 | |((( | ||
| 16 | Before phase 1 | ||
| 17 | )))|((( | ||
| 18 | Graph Transformer | ||
| 19 | Comment Preprocessor | ||
| 20 | Edge And Layer Constraint Edge Reverser | ||
| 21 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 22 | ((( | ||
| 23 | \\ | ||
| 24 | ))) | ||
| 25 | |((( | ||
| 26 | Before phase 2 | ||
| 27 | )))|((( | ||
| 28 | Label Dummy Inserter | ||
| 29 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 30 | ((( | ||
| 31 | |||
| 32 | ))) | ||
| 33 | |((( | ||
| 34 | Before phase 3 | ||
| 35 | )))|((( | ||
| 36 | Layer Constraint Processor | ||
| 37 | Hierarchical Port Constraint Processor | ||
| 38 | Long Edge Splitter | ||
| 39 | Port Side Processor | ||
| 40 | Label Dummy Switcher | ||
| 41 | Inverted Port Processor | ||
| 42 | Self Loop Processor | ||
| 43 | Port List Sorter | ||
| 44 | North South Port Preprocessor | ||
| 45 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 46 | ((( | ||
| 47 | |||
| 48 | \\\\\\\\ | ||
| 49 | ))) | ||
| 50 | |((( | ||
| 51 | Before phase 4 | ||
| 52 | )))|((( | ||
| 53 | In Layer Constraint Processor | ||
| 54 | Hierarchical Port Dummy Size Processor | ||
| 55 | Hyperedge Dummy Merger | ||
| 56 | Label Side Selector | ||
| 57 | Label And Node Size Processor | ||
| 58 | Node Margin Calculator | ||
| 59 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 60 | ((( | ||
| 61 | |||
| 62 | \\ | ||
| 63 | ))) | ||
| 64 | |((( | ||
| 65 | Before phase 5 | ||
| 66 | )))|((( | ||
| 67 | Layer Size and Graph Height Calculator | ||
| 68 | Hierarchical Port Position Processor | ||
| 69 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 70 | ((( | ||
| 71 | \\ | ||
| 72 | ))) | ||
| 73 | |((( | ||
| 74 | After phase 5 | ||
| 75 | )))|((( | ||
| 76 | Comment Postprocessor | ||
| 77 | Hypernode Processor | ||
| 78 | Hierarchical Port Orthogonal Edge Router | ||
| 79 | Long Edge Joiner | ||
| 80 | North South Port Postprocessor | ||
| 81 | Label Dummy Remover | ||
| 82 | Reversed Edge Restorer | ||
| 83 | Graph Transformer | ||
| 84 | End Label Processor | ||
| 85 | )))|(% colspan="1" %)(% colspan="1" %) | ||
| 86 | ((( | ||
| 87 | |||
| 88 | \\\\\\\\ | ||
| 89 | ))) |