Wiki source code of ESO to VHDL Testbench

Last modified by Richard Kreissig on 2023/09/14 11:12
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1 == The Testbench ==
2
3 ----
4
5 The testbench is a VHDL file which is used by ISE Simulator to test a VHDL component.
6
7 ISE is a programming an simulation tool to develop XILINX FPGAs. This work suite include a programminng workspace, a compiler, simulator (ISIM) and much more.
8
9 When you program a new component, you also want to test its behavior. But you do not always have an FPGA, so you could use a simulator. For that the simulator knows what input signals to simulate you need a so called tesbench.
10
11 A testbench lists the component you want to test e.g. abo. (You have written a vhdl file which behaves like ABO and this component is also called abo). It instantiate this componant as a Unit Under Test (UUT). This component (uut) will be tested with the input and outputs you have specified in a test process.
12
13 At first a testbench code example from ABO is shown for better understanding.
14
15 {{code linenumbers="true"}}
16 --/*****************************************************************************/
17 --/* G E N E R A T E D V H D L C O D E */
18 --/*****************************************************************************/
19 --/* KIELER - Kiel Integrated Environment for Layout Eclipse RichClient */
20 --/* */
21 --/* http://www.informatik.uni-kiel.de/rtsys/kieler/ */
22 --/* Copyright 2013 by */
23 --/* + Christian-Albrechts-University of Kiel */
24 --/* + Department of Computer Science */
25 --/* + Real-Time and Embedded Systems Group */
26 --/* */
27 --/* This code is provided under the terms of the Eclipse Public License (EPL).*/
28 --/*****************************************************************************/
29
30 LIBRARY ieee;
31 USE ieee.std_logic_1164.ALL;
32
33 ENTITY abo_tb IS
34 END abo_tb;
35
36 ARCHITECTURE behavior OF abo_tb IS
37
38 COMPONENT abo
39 PORT(
40 tick : IN std_logic;
41 reset : IN std_logic;
42 --inputs
43 A: IN boolean;
44 B: IN boolean;
45 --outputs
46 O1 : OUT boolean;
47 O2 : OUT boolean;
48 A_out : OUT boolean;
49 B_out : OUT boolean
50 );
51 END COMPONENT;
52
53 --Inputs
54 signal A : boolean := false;
55 signal B : boolean := false;
56
57 --Outputs
58 signal O1 : boolean := false;
59 signal O2 : boolean := false;
60 signal A_out : boolean := false;
61 signal B_out : boolean := false;
62
63 --Control
64 signal reset : std_logic := '0';
65 signal tick : std_logic := '0';
66 constant tick_period : time := 100 ns;
67
68 BEGIN
69 uut: abo PORT MAP(
70 tick => tick,
71 reset => reset,
72 --Inputs
73 A => A,
74 B => B,
75 --Outputs
76 O1 => O1,
77 O2 => O2,
78 A_out => A_out,
79 B_out => B_out
80 );
81
82 tick_process: process
83 begin
84 tick <= '0';
85 wait for tick_period/2;
86 tick <= '1';
87 wait for tick_period/2;
88 end process;
89
90 -- Stimulus process
91 stim_proc: process
92 begin
93 wait for 1 ps;
94
95 --sim Process
96
97 --NEW TRACE
98 reset <= '1';
99 wait for tick_period;
100 reset <= '0';
101
102 -- tick 1
103 A <= true;
104 B <= false;
105 wait for tick_period;
106 assert( O1 = true )
107 report "1st trace: 1st tick: O1 should have been true"
108 severity ERROR;
109 assert( O2 = false )
110 report "1st trace: 1st tick: O2 should have been false"
111 severity ERROR;
112 assert( A_out = true )
113 report "1st trace: 1st tick: A_out should have been true"
114 severity ERROR;
115 assert( B_out = true )
116 report "1st trace: 1st tick: B_out should have been true"
117 severity ERROR;
118
119 -- tick 2
120 A <= false;
121 B <= false;
122 wait for tick_period;
123 assert( O1 = true )
124 report "1st trace: 2nd tick: O1 should have been true"
125 severity ERROR;
126 assert( O2 = false )
127 report "1st trace: 2nd tick: O2 should have been false"
128 severity ERROR;
129 assert( A_out = false )
130 report "1st trace: 2nd tick: A_out should have been false"
131 severity ERROR;
132 assert( B_out = false )
133 report "1st trace: 2nd tick: B_out should have been false"
134 severity ERROR;
135
136 -- tick 3
137 A <= false;
138 B <= true;
139 wait for tick_period;
140 assert( O1 = false )
141 report "1st trace: 3rd tick: O1 should have been false"
142 severity ERROR;
143 assert( O2 = true )
144 report "1st trace: 3rd tick: O2 should have been true"
145 severity ERROR;
146 assert( A_out = false )
147 report "1st trace: 3rd tick: A_out should have been false"
148 severity ERROR;
149 assert( B_out = true )
150 report "1st trace: 3rd tick: B_out should have been true"
151 severity ERROR;
152
153 --NEW TRACE
154 reset <= '1';
155 wait for tick_period;
156 reset <= '0';
157
158 -- tick 1
159 A <= false;
160 B <= false;
161 wait for tick_period;
162 assert( O1 = false )
163 report "2nd trace: 1st tick: O1 should have been false"
164 severity ERROR;
165 assert( O2 = false )
166 report "2nd trace: 1st tick: O2 should have been false"
167 severity ERROR;
168 assert( A_out = false )
169 report "2nd trace: 1st tick: A_out should have been false"
170 severity ERROR;
171 assert( B_out = false )
172 report "2nd trace: 1st tick: B_out should have been false"
173 severity ERROR;
174
175 -- tick 2
176 A <= true;
177 B <= false;
178 wait for tick_period;
179 assert( O1 = false )
180 report "2nd trace: 2nd tick: O1 should have been false"
181 severity ERROR;
182 assert( O2 = true )
183 report "2nd trace: 2nd tick: O2 should have been true"
184 severity ERROR;
185 assert( A_out = true )
186 report "2nd trace: 2nd tick: A_out should have been true"
187 severity ERROR;
188 assert( B_out = true )
189 report "2nd trace: 2nd tick: B_out should have been true"
190 severity ERROR;
191 wait;
192 end process;
193
194 END;
195
196
197 {{/code}}
198
199 === Explanation: ===
200
201 Line 23: ABO component declaration
202
203 (% style="margin-left: 30.0px;" %)
204 Here the ABO component is declared, so the testbanch knows which component to test.
205
206 Line 38: declaration of local signals
207
208 (% style="margin-left: 30.0px;" %)
209 Local signals are needed for internal communication and for interconnection between components and processes.
210
211 Line 55: instantiation of uut
212
213 (% style="margin-left: 30.0px;" %)
214 Here is ABO instantiated
215
216 Line 69: tick process
217
218 (% style="margin-left: 30.0px;" %)
219 The tick process simulates the tick. This signal is a kind of a clock signal. Its cycle duration is set in variable tick_period.
220
221 Line 79: the simulation process
222
223 (% style="text-align: left;margin-left: 30.0px;" %)
224 The main simulation process, here the input signals are set and the output signals are tested according to specifications in ESO file.
225
226 (% style="text-align: left;" %)
227 == Technical View ==
228
229 ----
230
231 Therefore the core ESO contains no information about input and output signals the proper SCL model is needed to generate the testbench.
232
233 The variable declaration must conform to the used variables in the ESO file, logically.
234
235 |=(((
236 SCL Model
237 )))|=(((
238 Core ESO File
239 )))|=(% colspan="1" %)(% colspan="1" %)
240 (((
241 ESO File
242 )))
243 |(((
244 {{code linenumbers="true" language="java"}}
245 module ABO
246 input A : boolean;
247 input B : boolean;
248 output O1 : boolean = false;
249 output O2 : boolean = false;
250 output A_out : boolean;
251 output B_out : boolean;
252 {
253 fork
254 __WaitAB_HandleA_WaitA:
255 if A then
256 A_out = true;
257 B = true;
258 B_out = true;
259 O1 = true;
260 goto __WaitAB_HandleA_DoneA;
261 end;
262 pause;
263 goto __WaitAB_HandleA_WaitA;
264 __WaitAB_HandleA_DoneA:
265 par
266 __WaitAB_HandleB_WaitB:
267 pause;
268 if ! B then
269 goto __WaitAB_HandleB_WaitB;
270 end;
271 B_out = true;
272 O1 = true;
273 join;
274 O1 = false;
275 O2 = true;
276 }
277 {{/code}}
278 )))|(((
279 {{code linenumbers="true" language="perl"}}
280 !reset ;
281 %% A : true
282 %% O1 : true
283 %% A_out : true
284 %% B_out : true
285 ;
286
287 %% O1 : true
288 ;
289
290 %% B : true
291 %% O2 : true
292 %% B_out : true
293 ;
294
295 !reset ;
296 ;
297
298 %% A : true
299 %% O2 : true
300 %% A_out : true
301 %% B_out : true
302 ;
303 {{/code}}
304 )))|(% colspan="1" %)(% colspan="1" %)
305 (((
306 {{code linenumbers="true" language="perl"}}
307 !reset ;
308 A
309 % Output : O1 A_out B_out
310 ;
311 % Output : O1
312 ;
313 B
314 % Output : O2 B_out
315 ;
316 !reset ;
317 % Output :
318 ;
319 A
320 % Output : O2 A_out B_out
321 ;
322 {{/code}}
323 )))
324
325 {{info}}
326 SCL file is not realy correct, will be corrected as soon as possible
327 {{/info}}
328
329 The lines 23 to 66 (testbench file) were generated from the SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is needed for code generation.
330
331
332 The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be shown at the following example:
333
334 |=(% colspan="1" %)(% colspan="1" %)
335 (((
336 SCL
337 )))|=(((
338 ESO trace
339 )))|=(% colspan="1" %)(% colspan="1" %)
340 (((
341 Testbench
342 )))
343 |(% colspan="1" %)(% colspan="1" %)
344 (((
345 {{code linenumbers="true" language="java"}}
346 module test
347 input A ;
348 input B : boolean = false;
349 input B_value : integer = 0;
350 input C :boolean = false;
351 input C_value :boolean = false;
352 output D;
353 output E : boolean = false;
354 output E_value : integer = 5;
355 output F : boolean = false;
356 output F_value : boolean = false;
357 {
358 //pause;
359 }
360 {{/code}}
361 )))|(((
362 {{code linenumbers="true" language="perl"}}
363 !reset;
364 A C(false)
365 %Output: D F(false)
366 ;
367 {{/code}}
368
369 normally the core ESO is used, but for better unterstanding we use the normal ESO trace
370
371
372 )))|(% colspan="1" %)(% colspan="1" %)
373 (((
374 {{code linenumbers="true" language="java"}}
375 A <= true;
376 B <= false;
377 C <= true;
378 C_value <= false;
379 wait for tick_period;
380 assert( D = true )
381 report "1st trace: 1st tick: D should have been true"
382 severity ERROR;
383 assert( E = false )
384 report "1st trace: 1st tick: E should have been false"
385 severity ERROR;
386 assert( F = true )
387 report "1st trace: 1st tick: F should have been true"
388 severity ERROR;
389 assert( F_value = false )
390 report "1st trace: 1st tick: F_value should have been false"
391 severity ERROR;
392 {{/code}}
393 )))
394
395 **Set inputs**
396
397 Line 2 and 3 in the testbench are setting the inputs. All (!) inputs must be set!
398
399 * Pure signal which are present are set to the according value, e.g. //A<=true;//
400 * Valued signals which are present are set to their according value e.g. //C_value <= false;// and set present //B<=true;//
401 * ABSENT values (not listed in ESO files inputs) must be set absent
402 ** pure singals (not listed) e.g. K <= false
403 ** valued signals e.g. //B <= false//, only the present value will be set, the valued signal is not touched
404
405 **Wait for the tick to pass by**
406
407 The code //wait for tick_period;// waits for one tick, so the Hardware can compute the output values.
408
409 **Test Outputs**
410
411 After the tick has passed by we must check if the hardware computes the correct outputs. This is done by assertions. Every (!) output must be tested!
412
413 * Pure signals: Test the pure output signal according to the current ESO tick, if listed in the tick, e.g. //assert( D = true )//. If it is not specified in the trace test for absence,
414 * Valued signals: For valued signals, that are specified in the current ESO tick, test the present singal and the valued signal, e.g.// assert( F = true ) //and// assert( F_value = false)//
415 * Valued signals, which are not listed in the current tick in the ESO file: test only the present flag for absence (We can say anything about absent valued signals)
416
417 If an assertion failed the corresponding error will be printed to a log file. The severity level tells the simulator to go on with the simulation although an error occur.
418
419

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