Wiki source code of ESO to VHDL Testbench

Version 4.1 by gjo on 2013/07/04 12:07
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1 == The Testbench ==
2
3 ----
4
5 The testbench is a VHDL file wich is used by ISE Simulator to test a VHDL component.
6
7 ISE is a programming an simulation tool to develop XILINX FPGAs. This work suite include a programminng workspace, a compiler, simulator (ISIM) and much more.
8
9 When you program a new component, aou also want to test its behavior. But you always have an FPGA, so you can use a simulator. So that the simulator knows what input signals to simulate you need a so called tesbench.
10
11 A testbench lists the component you want to test e.g. abo. (You have written a vhdl file which behaves like ABO and this component is also called abo). And it instantiate this componant as a Unit Under Test (UUT). This component (uut) will be tested with the input and outputs you have specified later in a test process.
12
13 At first a testbench code example from ABO for better understanding.
14
15 {{code linenumbers="true"}}
16 --/*****************************************************************************/
17 --/* G E N E R A T E D V H D L C O D E */
18 --/*****************************************************************************/
19 --/* KIELER - Kiel Integrated Environment for Layout Eclipse RichClient */
20 --/* */
21 --/* http://www.informatik.uni-kiel.de/rtsys/kieler/ */
22 --/* Copyright 2013 by */
23 --/* + Christian-Albrechts-University of Kiel */
24 --/* + Department of Computer Science */
25 --/* + Real-Time and Embedded Systems Group */
26 --/* */
27 --/* This code is provided under the terms of the Eclipse Public License (EPL).*/
28 --/*****************************************************************************/
29
30 LIBRARY ieee;
31 USE ieee.std_logic_1164.ALL;
32
33 ENTITY abo_tb IS
34 END abo_tb;
35
36 ARCHITECTURE behavior OF abo_tb IS
37
38 COMPONENT abo
39 PORT(
40 tick : IN std_logic;
41 reset : IN std_logic;
42 --inputs
43 A: IN boolean;
44 B: IN boolean;
45 --outputs
46 O1 : OUT boolean;
47 O2 : OUT boolean;
48 A_out : OUT boolean;
49 B_out : OUT boolean
50 );
51 END COMPONENT;
52
53 --Inputs
54 signal A : boolean := false;
55 signal B : boolean := false;
56
57 --Outputs
58 signal O1 : boolean := false;
59 signal O2 : boolean := false;
60 signal A_out : boolean := false;
61 signal B_out : boolean := false;
62
63 --Control
64 signal reset : std_logic := '0';
65 signal tick : std_logic := '0';
66 constant tick_period : time := 100 ns;
67
68 BEGIN
69
70 uut: abo PORT MAP(
71 tick => tick,
72 reset => reset,
73 --Inputs
74 A => A,
75 B => B,
76 --Outputs
77 O1 => O1,
78 O2 => O2,
79 A_out => A_out,
80 B_out => B_out
81 );
82
83
84 tick_process: process
85 begin
86 tick <= '0';
87 wait for tick_period/2;
88 tick <= '1';
89 wait for tick_period/2;
90 end process;
91
92
93 -- Stimulus process
94 stim_proc: process
95 begin
96 wait for 1 ps;
97
98 --sim Process
99
100
101 --NEW TRACE
102 reset <= '1';
103 wait for tick_period;
104 reset <= '0';
105
106 -- tick 1
107 A <= true;
108 B <= false;
109 wait for tick_period;
110 assert( O1 = true )
111 report "1st trace: 1st tick: O1 should have been true"
112 severity ERROR;
113 assert( O2 = false )
114 report "1st trace: 1st tick: O2 should have been false"
115 severity ERROR;
116 assert( A_out = true )
117 report "1st trace: 1st tick: A_out should have been true"
118 severity ERROR;
119 assert( B_out = true )
120 report "1st trace: 1st tick: B_out should have been true"
121 severity ERROR;
122
123 -- tick 2
124 A <= false;
125 B <= false;
126 wait for tick_period;
127 assert( O1 = true )
128 report "1st trace: 2nd tick: O1 should have been true"
129 severity ERROR;
130 assert( O2 = false )
131 report "1st trace: 2nd tick: O2 should have been false"
132 severity ERROR;
133 assert( A_out = false )
134 report "1st trace: 2nd tick: A_out should have been false"
135 severity ERROR;
136 assert( B_out = false )
137 report "1st trace: 2nd tick: B_out should have been false"
138 severity ERROR;
139
140 -- tick 3
141 A <= false;
142 B <= true;
143 wait for tick_period;
144 assert( O1 = false )
145 report "1st trace: 3rd tick: O1 should have been false"
146 severity ERROR;
147 assert( O2 = true )
148 report "1st trace: 3rd tick: O2 should have been true"
149 severity ERROR;
150 assert( A_out = false )
151 report "1st trace: 3rd tick: A_out should have been false"
152 severity ERROR;
153 assert( B_out = true )
154 report "1st trace: 3rd tick: B_out should have been true"
155 severity ERROR;
156
157 --NEW TRACE
158 reset <= '1';
159 wait for tick_period;
160 reset <= '0';
161
162 -- tick 1
163 A <= false;
164 B <= false;
165 wait for tick_period;
166 assert( O1 = false )
167 report "2nd trace: 1st tick: O1 should have been false"
168 severity ERROR;
169 assert( O2 = false )
170 report "2nd trace: 1st tick: O2 should have been false"
171 severity ERROR;
172 assert( A_out = false )
173 report "2nd trace: 1st tick: A_out should have been false"
174 severity ERROR;
175 assert( B_out = false )
176 report "2nd trace: 1st tick: B_out should have been false"
177 severity ERROR;
178
179 -- tick 2
180 A <= true;
181 B <= false;
182 wait for tick_period;
183 assert( O1 = false )
184 report "2nd trace: 2nd tick: O1 should have been false"
185 severity ERROR;
186 assert( O2 = true )
187 report "2nd trace: 2nd tick: O2 should have been true"
188 severity ERROR;
189 assert( A_out = true )
190 report "2nd trace: 2nd tick: A_out should have been true"
191 severity ERROR;
192 assert( B_out = true )
193 report "2nd trace: 2nd tick: B_out should have been true"
194 severity ERROR;
195 wait;
196 end process;
197
198 END;
199
200
201 {{/code}}
202
203 === Explanation: ===
204
205 Line 23: ABO component declaration
206
207 (% style="margin-left: 30.0px;" %)
208 Here the ABO component is declared, so the testbanch knows which component to test.
209
210 Line 38: declaration of local signals
211
212 (% style="margin-left: 30.0px;" %)
213 Local signals are needed for internal communication and for interconnection between components and processes.
214
215 Line 55: instantiation of uut
216
217 (% style="margin-left: 30.0px;" %)
218 Here ABO is instantiated
219
220 Line 69: tick process
221
222 (% style="margin-left: 30.0px;" %)
223 The tick process simulates the tick. This signal is a kind of clock signal. Its cycle duration is set in variable tick_period.
224
225 Line 79: the simulation process
226
227 (% style="text-align: left;margin-left: 30.0px;" %)
228 The main simulation process, here the input signals are set and the output signals are tested according to specifications in ESO file.
229
230 (% style="text-align: left;" %)
231 == Technical View ==
232
233 ----
234
235 Therefor the core ESO contains no information about input and output signals the proper SCL model is needed to generate the testbench.
236
237 The variable declaration must fit to the used variables in the ESO file, logically.
238
239 |=(((
240 SCL Model
241 )))|=(((
242 Core ESO File
243 )))|=(% colspan="1" %)(% colspan="1" %)
244 (((
245 ESO File
246 )))
247 |(((
248 {{code linenumbers="true" language="java"}}
249 module ABO
250 input A : boolean;
251 input B : boolean;
252 output O1 : boolean = false;
253 output O2 : boolean = false;
254 output A_out : boolean;
255 output B_out : boolean;
256 {
257 fork
258 __WaitAB_HandleA_WaitA:
259 if A then
260 A_out = true;
261 B = true;
262 B_out = true;
263 O1 = true;
264 goto __WaitAB_HandleA_DoneA;
265 end;
266 pause;
267 goto __WaitAB_HandleA_WaitA;
268 __WaitAB_HandleA_DoneA:
269 par
270 __WaitAB_HandleB_WaitB:
271 pause;
272 if ! B then
273 goto __WaitAB_HandleB_WaitB;
274 end;
275 B_out = true;
276 O1 = true;
277 join;
278 O1 = false;
279 O2 = true;
280 }
281 {{/code}}
282 )))|(((
283 {{code linenumbers="true" language="perl"}}
284 !reset ;
285 %% A : true
286 %% O1 : true
287 %% A_out : true
288 %% B_out : true
289 ;
290
291 %% O1 : true
292 ;
293
294 %% B : true
295 %% O2 : true
296 %% B_out : true
297 ;
298
299 !reset ;
300 ;
301
302 %% A : true
303 %% O2 : true
304 %% A_out : true
305 %% B_out : true
306 ;
307 {{/code}}
308 )))|(% colspan="1" %)(% colspan="1" %)
309 (((
310 {{code linenumbers="true" language="perl"}}
311 !reset ;
312 A
313 % Output : O1 A_out B_out
314 ;
315 % Output : O1
316 ;
317 B
318 % Output : O2 B_out
319 ;
320 !reset ;
321 % Output :
322 ;
323 A
324 % Output : O2 A_out B_out
325 ;
326 {{/code}}
327 )))
328
329 {{note}}
330 SCL file is not realy correct, will be corrected as soon as possible
331 {{/note}}
332
333 The lines 23 to 66 (testbench file) are generated from SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is loaded and the needed code is generated.
334
335
336
337 The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be schown at the follwing example:
338
339 |=(% colspan="1" %)(% colspan="1" %)
340 (((
341 SCL
342 )))|=(((
343 ESO trace
344 )))|=(% colspan="1" %)(% colspan="1" %)
345 (((
346 Testbench
347 )))
348 |(% colspan="1" %)(% colspan="1" %)
349 (((
350 {{code linenumbers="true" language="java"}}
351 module test
352 input A ;
353 input B : boolean = false;
354 input B_value : integer = 0;
355 input C :boolean = false;
356 input C_value :boolean = false;
357 output D;
358 output E : boolean = false;
359 output E_value : integer = 5;
360 output F : boolean = false;
361 output F_value : boolean = false;
362 {
363 //pause;
364 }
365 {{/code}}
366 )))|(((
367 {{code linenumbers="true" language="perl"}}
368 !reset;
369 A C(false)
370 %Output: D F(false)
371 ;
372 {{/code}}
373
374 normally the core ESO is used, but
375
376 for better unterstanding we use the
377
378 normal ESO trace
379
380
381 )))|(% colspan="1" %)(% colspan="1" %)
382 (((
383 {{code linenumbers="true" language="java"}}
384 A <= true;
385 B <= false;
386 C <= true;
387 C_value <= false;
388 wait for tick_period;
389 assert( D = true )
390 report "1st trace: 1st tick: D should have been true"
391 severity ERROR;
392 assert( E = false )
393 report "1st trace: 1st tick: E should have been false"
394 severity ERROR;
395 assert( F = true )
396 report "1st trace: 1st tick: F should have been true"
397 severity ERROR;
398 assert( F_value = false )
399 report "1st trace: 1st tick: F_value should have been false"
400 severity ERROR;
401 {{/code}}
402 )))
403
404 **Set inputs**
405
406 Line 2 and 3 in the testbench are setting the inpute. All (!) inputs must be set!
407
408 * Pure signal which are present are set to the according value, e.g. //A<=true;//
409 * Valued signals which are present are set to thier according value e.g. //C_value <= false;// and set present //B<=true;//
410 * ABSENT values (not listed in ESO files inputs) mus be set absent
411 ** pure singals (not listeg) e.g. K <= false
412 ** valued signals e.g. //B <= false//, only the present value will be set, the valued signal is not touched
413
414 **Wait for the tick to pass by**
415
416 The code //wait for tick_period;// waits for one tick, so the Hardware can compute the output values.
417
418 **Test Outputs**
419
420 After the tick has passed by we must check if the hardware computes the correct outputs. This is done by assertions. Every (!) output must tested!
421
422 * Pure signals: Test the pure output signal according to the current ESO tick, if listed, e.g. //assert( D = true )//. If it is not specified in the trace test for absence,
423 * Valued signals: For valued signals that are specified in the current ESO tick test the present singal and the valued signal, e.g. //assert( F = true )// and //assert( F_value = false)//
424 * Valued signals which are not listed in the current tick in the ESO file: test only the present flag for absence (We cannot say anything about absent valued signals)
425
426 If an assertion failed the corresponding error will be printed to a log file. The severity level tells the simulator to go on with the simulation altough an error acoored.
427
428
429
430
431
432

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