Wiki source code of ESO to VHDL Testbench

Version 1.1 by gjo on 2013/07/04 11:38
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1 == The Testbench ==
2
3 ----
4
5 The testbench is a VHDL file wich is used by ISE Simulator to test a VHDL component.
6
7 ISE is a programming an simulation tool to develop XILINX FPGAs. This work suite include a programminng workspace, a compiler, simulator (ISIM) and much more.
8
9 When you program a new component, aou also want to test its behavior. But you always have an FPGA, so you can use a simulator. So that the simulator knows what input signals to simulate you need a so called tesbench.
10
11 A testbench lists the component you want to test e.g. abo. (You have written a vhdl file which behaves like ABO and this component is also called abo). And it instantiate this componant as a Unit Under Test (UUT). This component (uut) will be tested with the input and outputs you have specified later in a test process.
12
13 At first a testbench code example from ABO for better understanding.
14
15 {{code linenumbers="true"}}
16
17 --/*****************************************************************************/
18 --/* G E N E R A T E D V H D L C O D E */
19 --/*****************************************************************************/
20 --/* KIELER - Kiel Integrated Environment for Layout Eclipse RichClient */
21 --/* */
22 --/* http://www.informatik.uni-kiel.de/rtsys/kieler/ */
23 --/* Copyright 2013 by */
24 --/* + Christian-Albrechts-University of Kiel */
25 --/* + Department of Computer Science */
26 --/* + Real-Time and Embedded Systems Group */
27 --/* */
28 --/* This code is provided under the terms of the Eclipse Public License (EPL).*/
29 --/*****************************************************************************/
30
31 LIBRARY ieee;
32 USE ieee.std_logic_1164.ALL;
33
34 ENTITY abo_tb IS
35 END abo_tb;
36
37 ARCHITECTURE behavior OF abo_tb IS
38
39 COMPONENT abo
40 PORT(
41 tick : IN std_logic;
42 reset : IN std_logic;
43 --inputs
44 A: IN boolean;
45 B: IN boolean;
46 --outputs
47 O1 : OUT boolean;
48 O2 : OUT boolean;
49 A_out : OUT boolean;
50 B_out : OUT boolean
51 );
52 END COMPONENT;
53
54 --Inputs
55 signal A : boolean := false;
56 signal B : boolean := false;
57
58 --Outputs
59 signal O1 : boolean := false;
60 signal O2 : boolean := false;
61 signal A_out : boolean := false;
62 signal B_out : boolean := false;
63
64 --Control
65 signal reset : std_logic := '0';
66 signal tick : std_logic := '0';
67 constant tick_period : time := 100 ns;
68
69 BEGIN
70
71 uut: abo PORT MAP(
72 tick => tick,
73 reset => reset,
74 --Inputs
75 A => A,
76 B => B,
77 --Outputs
78 O1 => O1,
79 O2 => O2,
80 A_out => A_out,
81 B_out => B_out
82 );
83
84
85 tick_process: process
86 begin
87 tick <= '0';
88 wait for tick_period/2;
89 tick <= '1';
90 wait for tick_period/2;
91 end process;
92
93
94 -- Stimulus process
95 stim_proc: process
96 begin
97 wait for 1 ps;
98
99 --sim Process
100
101
102 --NEW TRACE
103 reset <= '1';
104 wait for tick_period;
105 reset <= '0';
106
107 -- tick 1
108 A <= true;
109 B <= false;
110 wait for tick_period;
111 assert( O1 = true )
112 report "1st trace: 1st tick: O1 should have been true"
113 severity ERROR;
114 assert( O2 = false )
115 report "1st trace: 1st tick: O2 should have been false"
116 severity ERROR;
117 assert( A_out = true )
118 report "1st trace: 1st tick: A_out should have been true"
119 severity ERROR;
120 assert( B_out = true )
121 report "1st trace: 1st tick: B_out should have been true"
122 severity ERROR;
123
124 -- tick 2
125 A <= false;
126 B <= false;
127 wait for tick_period;
128 assert( O1 = true )
129 report "1st trace: 2nd tick: O1 should have been true"
130 severity ERROR;
131 assert( O2 = false )
132 report "1st trace: 2nd tick: O2 should have been false"
133 severity ERROR;
134 assert( A_out = false )
135 report "1st trace: 2nd tick: A_out should have been false"
136 severity ERROR;
137 assert( B_out = false )
138 report "1st trace: 2nd tick: B_out should have been false"
139 severity ERROR;
140
141 -- tick 3
142 A <= false;
143 B <= true;
144 wait for tick_period;
145 assert( O1 = false )
146 report "1st trace: 3rd tick: O1 should have been false"
147 severity ERROR;
148 assert( O2 = true )
149 report "1st trace: 3rd tick: O2 should have been true"
150 severity ERROR;
151 assert( A_out = false )
152 report "1st trace: 3rd tick: A_out should have been false"
153 severity ERROR;
154 assert( B_out = true )
155 report "1st trace: 3rd tick: B_out should have been true"
156 severity ERROR;
157
158 --NEW TRACE
159 reset <= '1';
160 wait for tick_period;
161 reset <= '0';
162
163 -- tick 1
164 A <= false;
165 B <= false;
166 wait for tick_period;
167 assert( O1 = false )
168 report "2nd trace: 1st tick: O1 should have been false"
169 severity ERROR;
170 assert( O2 = false )
171 report "2nd trace: 1st tick: O2 should have been false"
172 severity ERROR;
173 assert( A_out = false )
174 report "2nd trace: 1st tick: A_out should have been false"
175 severity ERROR;
176 assert( B_out = false )
177 report "2nd trace: 1st tick: B_out should have been false"
178 severity ERROR;
179
180 -- tick 2
181 A <= true;
182 B <= false;
183 wait for tick_period;
184 assert( O1 = false )
185 report "2nd trace: 2nd tick: O1 should have been false"
186 severity ERROR;
187 assert( O2 = true )
188 report "2nd trace: 2nd tick: O2 should have been true"
189 severity ERROR;
190 assert( A_out = true )
191 report "2nd trace: 2nd tick: A_out should have been true"
192 severity ERROR;
193 assert( B_out = true )
194 report "2nd trace: 2nd tick: B_out should have been true"
195 severity ERROR;
196 wait;
197 end process;
198
199 END;
200
201
202 {{/code}}
203
204 === Explanation: ===
205
206 Line 23: ABO component declaration
207
208 (% style="margin-left: 30.0px;" %)
209 Here the ABO component is declared, so the testbanch knows which component to test.
210
211 Line 38: declaration of local signals
212
213 (% style="margin-left: 30.0px;" %)
214 Local signals are needed for internal communication and for interconnection between components and processes.
215
216 Line 55: instantiation of uut
217
218 (% style="margin-left: 30.0px;" %)
219 Here ABO is instantiated
220
221 Line 69: tick process
222
223 (% style="margin-left: 30.0px;" %)
224 The tick process simulates the tick. This signal is a kind of clock signal. Its cycle duration is set in variable tick_period.
225
226 Line 79: the simulation process
227
228 (% style="text-align: left;margin-left: 30.0px;" %)
229 The main simulation process, here the input signals are set and the output signals are tested according to specifications in ESO file.
230
231 (% style="text-align: left;" %)
232 == Technical View ==
233
234 ----
235
236 Therefor the core ESO contains no information about input and output signals the proper SCL model is needed to generate the testbench.
237
238 The variable declaration must fit to the used variables in the ESO file, logically.
239
240 |=(((
241 SCL Model
242 )))|=(((
243 Core ESO file
244 )))
245 |(((
246 {{code linenumbers="true" language="java"}}
247 module ABO
248 input A : boolean;
249 input B : boolean;
250 output O1 : boolean = false;
251 output O2 : boolean = false;
252 output A_out : boolean;
253 output B_out : boolean;
254 {
255 fork
256 __WaitAB_HandleA_WaitA:
257 if A then
258 A_out = true;
259 B = true;
260 B_out = true;
261 O1 = true;
262 goto __WaitAB_HandleA_DoneA;
263 end;
264 pause;
265 goto __WaitAB_HandleA_WaitA;
266 __WaitAB_HandleA_DoneA:
267 par
268 __WaitAB_HandleB_WaitB:
269 pause;
270 if ! B then
271 goto __WaitAB_HandleB_WaitB;
272 end;
273 B_out = true;
274 O1 = true;
275 join;
276 O1 = false;
277 O2 = true;
278 }
279 {{/code}}
280 )))|(((
281 {{code linenumbers="true" language="perl"}}
282 !reset ;
283 %% A : true
284 %% O1 : true
285 %% A_out : true
286 %% B_out : true
287 ;
288
289 %% O1 : true
290 ;
291
292 %% B : true
293 %% O2 : true
294 %% B_out : true
295 ;
296
297 !reset ;
298 ;
299
300 %% A : true
301 %% O2 : true
302 %% A_out : true
303 %% B_out : true
304 ;
305 {{/code}}
306 )))
307
308 {{note}}
309 SCL file is not realy correct, will be corrected as soon as possible
310 {{/note}}
311
312 The lines 23 to 66 (testbench file) are generated from SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is loaded and the needed code is generated.
313
314 The simulation process (starts at line 79) is genrates using the core ESO file.
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324

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