Changes for page ESO to VHDL Testbench

Last modified by Richard Kreissig on 2023/09/14 11:12
<
From version < 5.1 >
edited by gjo
on 2013/07/04 12:49
To version < 3.1 >
edited by gjo
on 2013/07/04 11:51
>
Change comment: There is no comment for this version

Summary

Details

Page properties
Content
... ... @@ -2,15 +2,15 @@
2 2  
3 3  ----
4 4  
5 -The testbench is a VHDL file which is used by ISE Simulator to test a VHDL component.
5 +The testbench is a VHDL file wich is used by ISE Simulator to test a VHDL component.
6 6  
7 7  ISE is a programming an simulation tool to develop XILINX FPGAs. This work suite include a programminng workspace, a compiler, simulator (ISIM) and much more.
8 8  
9 -When you program a new component, you also want to test its behavior. But you do not always have an FPGA, so you could use a simulator. For that the simulator knows what input signals to simulate you need a so called tesbench.
9 +When you program a new component, aou also want to test its behavior. But you always have an FPGA, so you can use a simulator. So that the simulator knows what input signals to simulate you need a so called tesbench.
10 10  
11 -A testbench lists the component you want to test e.g. abo. (You have written a vhdl file which behaves like ABO and this component is also called abo). It instantiate this componant as a Unit Under Test (UUT). This component (uut) will be tested with the input and outputs you have specified in a test process.
11 +A testbench lists the component you want to test e.g. abo. (You have written a vhdl file which behaves like ABO and this component is also called abo). And it instantiate this componant as a Unit Under Test (UUT). This component (uut) will be tested with the input and outputs you have specified later in a test process.
12 12  
13 -At first a testbench code example from ABO is shown for better understanding.
13 +At first a testbench code example from ABO for better understanding.
14 14  
15 15  {{code linenumbers="true"}}
16 16  --/*****************************************************************************/
... ... @@ -66,6 +66,7 @@
66 66  constant tick_period : time := 100 ns;
67 67  
68 68  BEGIN
69 +
69 69   uut: abo PORT MAP(
70 70   tick => tick,
71 71   reset => reset,
... ... @@ -79,6 +79,7 @@
79 79   B_out => B_out
80 80   );
81 81  
83 +
82 82   tick_process: process
83 83   begin
84 84   tick <= '0';
... ... @@ -87,6 +87,7 @@
87 87   wait for tick_period/2;
88 88   end process;
89 89  
92 +
90 90   -- Stimulus process
91 91   stim_proc: process
92 92   begin
... ... @@ -94,6 +94,7 @@
94 94  
95 95   --sim Process
96 96  
100 +
97 97   --NEW TRACE
98 98   reset <= '1';
99 99   wait for tick_period;
... ... @@ -211,12 +211,12 @@
211 211  Line 55: instantiation of uut
212 212  
213 213  (% style="margin-left: 30.0px;" %)
214 -Here is ABO instantiated
218 +Here ABO is instantiated
215 215  
216 216  Line 69: tick process
217 217  
218 218  (% style="margin-left: 30.0px;" %)
219 -The tick process simulates the tick. This signal is a kind of a clock signal. Its cycle duration is set in variable tick_period.
223 +The tick process simulates the tick. This signal is a kind of clock signal. Its cycle duration is set in variable tick_period.
220 220  
221 221  Line 79: the simulation process
222 222  
... ... @@ -228,9 +228,9 @@
228 228  
229 229  ----
230 230  
231 -Therefore the core ESO contains no information about input and output signals the proper SCL model is needed to generate the testbench.
235 +Therefor the core ESO contains no information about input and output signals the proper SCL model is needed to generate the testbench.
232 232  
233 -The variable declaration must conform to the used variables in the ESO file, logically.
237 +The variable declaration must fit to the used variables in the ESO file, logically.
234 234  
235 235  |=(((
236 236  SCL Model
... ... @@ -326,44 +326,23 @@
326 326  SCL file is not realy correct, will be corrected as soon as possible
327 327  {{/note}}
328 328  
329 -The lines 23 to 66 (testbench file) were generated from the SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is needed for code generation.
333 +The lines 23 to 66 (testbench file) are generated from SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is loaded and the needed code is generated.
330 330  
331 331  
332 332  
333 -The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be shown at the following example:
337 +The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be schown at the follwing example:
334 334  
335 -|=(% colspan="1" %)(% colspan="1" %)
336 -(((
337 -SCL
338 -)))|=(((
339 +|=(((
339 339  ESO trace
340 340  )))|=(% colspan="1" %)(% colspan="1" %)
341 341  (((
342 342  Testbench
343 343  )))
344 -|(% colspan="1" %)(% colspan="1" %)
345 -(((
346 -{{code linenumbers="true" language="java"}}
347 -module test
348 -input A ;
349 -input B : boolean = false;
350 -input B_value : integer = 0;
351 -input C :boolean = false;
352 -input C_value :boolean = false;
353 -output D;
354 -output E : boolean = false;
355 -output E_value : integer = 5;
356 -output F : boolean = false;
357 -output F_value : boolean = false;
358 -{
359 - //pause;
360 -}
361 -{{/code}}
362 -)))|(((
345 +|(((
363 363  {{code linenumbers="true" language="perl"}}
364 364  !reset;
365 -A C(false)
366 -%Output: D F(false)
348 +A B(5) C(false)
349 +%Output: D E(3) F(false)
367 367  ;
368 368  {{/code}}
369 369  
... ... @@ -376,6 +376,12 @@
376 376  
377 377  )))|(% colspan="1" %)(% colspan="1" %)
378 378  (((
362 +
363 +
364 +
365 +
366 +
367 +
379 379  {{code linenumbers="true" language="java"}}
380 380  A <= true;
381 381  B <= false;
... ... @@ -395,32 +395,20 @@
395 395   report "1st trace: 1st tick: F_value should have been false"
396 396   severity ERROR;
397 397  {{/code}}
398 -)))
399 399  
400 -**Set inputs**
388 +
401 401  
402 -Line 2 and 3 in the testbench are setting the inputs. All (!) inputs must be set!
390 +
403 403  
404 -* Pure signal which are present are set to the according value, e.g. //A<=true;//
405 -* Valued signals which are present are set to their according value e.g. //C_value <= false;// and set present //B<=true;//
406 -* ABSENT values (not listed in ESO files inputs) must be set absent
407 -** pure singals (not listed) e.g. K <= false
408 -** valued signals e.g. //B <= false//, only the present value will be set, the valued signal is not touched
392 +
393 +)))
409 409  
410 -**Wait for the tick to pass by**
395 +Line 2 and 3 in the testbench are setting the inpute. All (!) inputs must be set! Signal which are present are set to the according value
411 411  
412 -The code //wait for tick_period;// waits for one tick, so the Hardware can compute the output values.
397 +
413 413  
414 -**Test Outputs**
399 +
415 415  
416 -After the tick has passed by we must check if the hardware computes the correct outputs. This is done by assertions. Every (!) output must be tested!
417 -
418 -* Pure signals: Test the pure output signal according to the current ESO tick, if listed in the tick, e.g. //assert( D = true )//. If it is not specified in the trace test for absence,
419 -* Valued signals: For valued signals, that are specified in the current ESO tick, test the present singal and the valued signal, e.g.// assert( F = true ) //and// assert( F_value = false)//
420 -* Valued signals, which are not listed in the current tick in the ESO file: test only the present flag for absence (We can say anything about absent valued signals)
421 -
422 -If an assertion failed the corresponding error will be printed to a log file. The severity level tells the simulator to go on with the simulation although an error occur.
423 -
424 424  
425 425  
426 426  
Confluence.Code.ConfluencePageClass[0]
Id
... ... @@ -1,1 +1,1 @@
1 -7111275
1 +7111244
URL
... ... @@ -1,1 +1,1 @@
1 -https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/KIELER/pages/7111275/ESO to VHDL Testbench
1 +https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/KIELER/pages/7111244/ESO to VHDL Testbench

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