Changes for page ESO to VHDL Testbench

Last modified by Richard Kreissig on 2023/09/14 11:12
From version < 4.1 >
edited by gjo
on 2013/07/04 12:07
To version 1.1 >
edited by gjo
on 2013/07/04 11:38
>
Change comment: There is no comment for this version

Summary

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Content
... ... @@ -13,6 +13,7 @@
13 13  At first a testbench code example from ABO for better understanding.
14 14  
15 15  {{code linenumbers="true"}}
16 +
16 16  --/*****************************************************************************/
17 17  --/* G E N E R A T E D V H D L C O D E */
18 18  --/*****************************************************************************/
... ... @@ -239,10 +239,7 @@
239 239  |=(((
240 240  SCL Model
241 241  )))|=(((
242 -Core ESO File
243 -)))|=(% colspan="1" %)(% colspan="1" %)
244 -(((
245 -ESO File
243 +Core ESO file
246 246  )))
247 247  |(((
248 248  {{code linenumbers="true" language="java"}}
... ... @@ -305,25 +305,6 @@
305 305  %% B_out : true
306 306  ;
307 307  {{/code}}
308 -)))|(% colspan="1" %)(% colspan="1" %)
309 -(((
310 -{{code linenumbers="true" language="perl"}}
311 -!reset ;
312 -A
313 -% Output : O1 A_out B_out
314 -;
315 -% Output : O1
316 -;
317 -B
318 -% Output : O2 B_out
319 -;
320 -!reset ;
321 -% Output :
322 -;
323 -A
324 -% Output : O2 A_out B_out
325 -;
326 -{{/code}}
327 327  )))
328 328  
329 329  {{note}}
... ... @@ -332,99 +332,12 @@
332 332  
333 333  The lines 23 to 66 (testbench file) are generated from SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is loaded and the needed code is generated.
334 334  
314 +The simulation process (starts at line 79) is genrates using the core ESO file.
315 +
335 335  
336 336  
337 -The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be schown at the follwing example:
338 -
339 -|=(% colspan="1" %)(% colspan="1" %)
340 -(((
341 -SCL
342 -)))|=(((
343 -ESO trace
344 -)))|=(% colspan="1" %)(% colspan="1" %)
345 -(((
346 -Testbench
347 -)))
348 -|(% colspan="1" %)(% colspan="1" %)
349 -(((
350 -{{code linenumbers="true" language="java"}}
351 -module test
352 -input A ;
353 -input B : boolean = false;
354 -input B_value : integer = 0;
355 -input C :boolean = false;
356 -input C_value :boolean = false;
357 -output D;
358 -output E : boolean = false;
359 -output E_value : integer = 5;
360 -output F : boolean = false;
361 -output F_value : boolean = false;
362 -{
363 - //pause;
364 -}
365 -{{/code}}
366 -)))|(((
367 -{{code linenumbers="true" language="perl"}}
368 -!reset;
369 -A C(false)
370 -%Output: D F(false)
371 -;
372 -{{/code}}
373 -
374 -normally the core ESO is used, but
375 -
376 - for better unterstanding we use the
377 -
378 - normal ESO trace
379 -
380 380  
381 -)))|(% colspan="1" %)(% colspan="1" %)
382 -(((
383 -{{code linenumbers="true" language="java"}}
384 -A <= true;
385 -B <= false;
386 -C <= true;
387 -C_value <= false;
388 -wait for tick_period;
389 -assert( D = true )
390 - report "1st trace: 1st tick: D should have been true"
391 - severity ERROR;
392 -assert( E = false )
393 - report "1st trace: 1st tick: E should have been false"
394 - severity ERROR;
395 -assert( F = true )
396 - report "1st trace: 1st tick: F should have been true"
397 - severity ERROR;
398 -assert( F_value = false )
399 - report "1st trace: 1st tick: F_value should have been false"
400 - severity ERROR;
401 -{{/code}}
402 -)))
403 403  
404 -**Set inputs**
405 -
406 -Line 2 and 3 in the testbench are setting the inpute. All (!) inputs must be set!
407 -
408 -* Pure signal which are present are set to the according value, e.g. //A<=true;//
409 -* Valued signals which are present are set to thier according value e.g. //C_value <= false;// and set present //B<=true;//
410 -* ABSENT values (not listed in ESO files inputs) mus be set absent
411 -** pure singals (not listeg) e.g. K <= false
412 -** valued signals e.g. //B <= false//, only the present value will be set, the valued signal is not touched
413 -
414 -**Wait for the tick to pass by**
415 -
416 -The code //wait for tick_period;// waits for one tick, so the Hardware can compute the output values.
417 -
418 -**Test Outputs**
419 -
420 -After the tick has passed by we must check if the hardware computes the correct outputs. This is done by assertions. Every (!) output must tested!
421 -
422 -* Pure signals: Test the pure output signal according to the current ESO tick, if listed, e.g. //assert( D = true )//. If it is not specified in the trace test for absence,
423 -* Valued signals: For valued signals that are specified in the current ESO tick test the present singal and the valued signal, e.g. //assert( F = true )// and //assert( F_value = false)//
424 -* Valued signals which are not listed in the current tick in the ESO file: test only the present flag for absence (We cannot say anything about absent valued signals)
425 -
426 -If an assertion failed the corresponding error will be printed to a log file. The severity level tells the simulator to go on with the simulation altough an error acoored.
427 -
428 428  
429 429  
430 430  
Confluence.Code.ConfluencePageClass[0]
Id
... ... @@ -1,1 +1,1 @@
1 -7111257
1 +7111236
URL
... ... @@ -1,1 +1,1 @@
1 -https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/KIELER/pages/7111257/ESO to VHDL Testbench
1 +https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/KIELER/pages/7111236/ESO to VHDL Testbench

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