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...	...	@@ -336,17 +336,38 @@
336	336
337	337	The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be schown at the follwing example:
338	338
339		-|=(((
	339	+|=(% colspan="1" %)(% colspan="1" %)
	340	+(((
	341	+SCL
	342	+)))|=(((
340	340	ESO trace
341	341	)))|=(% colspan="1" %)(% colspan="1" %)
342	342	(((
343	343	Testbench
344	344	)))
345		-|(((
	348	+|(% colspan="1" %)(% colspan="1" %)
	349	+(((
	350	+{{code linenumbers="true" language="java"}}
	351	+module test
	352	+input A ;
	353	+input B : boolean = false;
	354	+input B_value : integer = 0;
	355	+input C :boolean = false;
	356	+input C_value :boolean = false;
	357	+output D;
	358	+output E : boolean = false;
	359	+output E_value : integer = 5;
	360	+output F : boolean = false;
	361	+output F_value : boolean = false;
	362	+{
	363	+ //pause;
	364	+}
	365	+{{/code}}
	366	+)))|(((
346	346	{{code linenumbers="true" language="perl"}}
347	347	!reset;
348		-A B(5) C(false)
349		-%Output: D E(3) F(false)
	369	+A C(false)
	370	+%Output: D F(false)
350	350	;
351	351	{{/code}}
352	352
...	...	@@ -359,12 +359,6 @@
359	359
360	360	)))|(% colspan="1" %)(% colspan="1" %)
361	361	(((
362		-
363		-
364		-
365		-
366		-
367		-
368	368	{{code linenumbers="true" language="java"}}
369	369	A <= true;
370	370	B <= false;
...	...	@@ -384,20 +384,32 @@
384	384	report "1st trace: 1st tick: F_value should have been false"
385	385	severity ERROR;
386	386	{{/code}}
	402	+)))
387	387
388		-
	404	+**Set inputs**
389	389
390		-
	406	+Line 2 and 3 in the testbench are setting the inpute. All (!) inputs must be set!
391	391
392		-
393		-)))
	408	+* Pure signal which are present are set to the according value, e.g. //A<=true;//
	409	+* Valued signals which are present are set to thier according value e.g. //C_value <= false;// and set present //B<=true;//
	410	+* ABSENT values (not listed in ESO files inputs) mus be set absent
	411	+** pure singals (not listeg) e.g. K <= false
	412	+** valued signals e.g. //B <= false//, only the present value will be set, the valued signal is not touched
394	394
395		-Line 2 and 3 in the testbench are setting the inpute. All (!) inputs must be set! Signal which are present are set to the according value
	414	+**Wait for the tick to pass by**
396	396
397		-
	416	+The code //wait for tick_period;// waits for one tick, so the Hardware can compute the output values.
398	398
399		-
	418	+**Test Outputs**
400	400
	420	+After the tick has passed by we must check if the hardware computes the correct outputs. This is done by assertions. Every (!) output must tested!
	421	+
	422	+* Pure signals: Test the pure output signal according to the current ESO tick, if listed, e.g. //assert( D = true )//. If it is not specified in the trace test for absence,
	423	+* Valued signals: For valued signals that are specified in the current ESO tick test the present singal and the valued signal, e.g. //assert( F = true )// and //assert( F_value = false)//
	424	+* Valued signals which are not listed in the current tick in the ESO file: test only the present flag for absence (We cannot say anything about absent valued signals)
	425	+
	426	+If an assertion failed the corresponding error will be printed to a log file. The severity level tells the simulator to go on with the simulation altough an error acoored.
	427	+
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Confluence.Code.ConfluencePageClass[0]

Id

...	...	@@ -1,1 +1,1 @@
1		-7111244
	1	+7111257

URL

...	...	@@ -1,1 +1,1 @@
1		-https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/KIELER/pages/7111244/ESO to VHDL Testbench
	1	+https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/KIELER/pages/7111257/ESO to VHDL Testbench