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Content

...	...	@@ -13,6 +13,7 @@
13	13	At first a testbench code example from ABO for better understanding.
14	14
15	15	{{code linenumbers="true"}}
	16	+
16	16	--/*****************************************************************************/
17	17	--/* G E N E R A T E D V H D L C O D E */
18	18	--/*****************************************************************************/
...	...	@@ -239,10 +239,7 @@
239	239	|=(((
240	240	SCL Model
241	241	)))|=(((
242		-Core ESO File
243		-)))|=(% colspan="1" %)(% colspan="1" %)
244		-(((
245		-ESO File
	243	+Core ESO file
246	246	)))
247	247	|(((
248	248	{{code linenumbers="true" language="java"}}
...	...	@@ -305,25 +305,6 @@
305	305	%% B_out : true
306	306	;
307	307	{{/code}}
308		-)))|(% colspan="1" %)(% colspan="1" %)
309		-(((
310		-{{code linenumbers="true" language="perl"}}
311		-!reset ;
312		-A
313		-% Output : O1 A_out B_out
314		-;
315		-% Output : O1
316		-;
317		-B
318		-% Output : O2 B_out
319		-;
320		-!reset ;
321		-% Output :
322		-;
323		-A
324		-% Output : O2 A_out B_out
325		-;
326		-{{/code}}
327	327	)))
328	328
329	329	{{note}}
...	...	@@ -332,74 +332,14 @@
332	332
333	333	The lines 23 to 66 (testbench file) are generated from SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is loaded and the needed code is generated.
334	334
335		-
	314	+The simulation process (starts at line 79) is genrates using the core ESO file.
336	336
337		-The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be schown at the follwing example:
338		-
339		-|=(((
340		-ESO trace
341		-)))|=(% colspan="1" %)(% colspan="1" %)
342		-(((
343		-Testbench
344		-)))
345		-|(((
346		-{{code linenumbers="true" language="perl"}}
347		-!reset;
348		-A B(5) C(false)
349		-%Output: D E(3) F(false)
350		-;
351		-{{/code}}
352		-
353		-normally the core ESO is used, but
354		-
355		- for better unterstanding we use the
356		-
357		- normal ESO trace
358		-
359	359
360		-)))|(% colspan="1" %)(% colspan="1" %)
361		-(((
362		-
363	363
364	364
365	365
366	366
367	367
368		-{{code linenumbers="true" language="java"}}
369		-A <= true;
370		-B <= false;
371		-C <= true;
372		-C_value <= false;
373		-wait for tick_period;
374		-assert( D = true )
375		- report "1st trace: 1st tick: D should have been true"
376		- severity ERROR;
377		-assert( E = false )
378		- report "1st trace: 1st tick: E should have been false"
379		- severity ERROR;
380		-assert( F = true )
381		- report "1st trace: 1st tick: F should have been true"
382		- severity ERROR;
383		-assert( F_value = false )
384		- report "1st trace: 1st tick: F_value should have been false"
385		- severity ERROR;
386		-{{/code}}
387		-
388	388
389	389
390	390
391		-
392		-
393		-)))
394		-
395		-Line 2 and 3 in the testbench are setting the inpute. All (!) inputs must be set! Signal which are present are set to the according value
396		-
397		-
398		-
399		-
400		-
401		-
402		-
403		-
404		-
405		-

Confluence.Code.ConfluencePageClass[0]

Id

...	...	@@ -1,1 +1,1 @@
1		-7111244
	1	+7111236

URL

...	...	@@ -1,1 +1,1 @@
1		-https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/KIELER/pages/7111244/ESO to VHDL Testbench
	1	+https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/KIELER/pages/7111236/ESO to VHDL Testbench