Changes for page ESO to VHDL Testbench

Last modified by Richard Kreissig on 2023/09/14 11:12
<
From version < 2.1 >
edited by gjo
on 2013/07/04 11:38
To version < 5.1 >
edited by gjo
on 2013/07/04 12:49
>
Change comment: There is no comment for this version

Summary

Details

Page properties
Content
... ... @@ -2,18 +2,17 @@
2 2  
3 3  ----
4 4  
5 -The testbench is a VHDL file wich is used by ISE Simulator to test a VHDL component.
5 +The testbench is a VHDL file which is used by ISE Simulator to test a VHDL component.
6 6  
7 7  ISE is a programming an simulation tool to develop XILINX FPGAs. This work suite include a programminng workspace, a compiler, simulator (ISIM) and much more.
8 8  
9 -When you program a new component, aou also want to test its behavior. But you always have an FPGA, so you can use a simulator. So that the simulator knows what input signals to simulate you need a so called tesbench.
9 +When you program a new component, you also want to test its behavior. But you do not always have an FPGA, so you could use a simulator. For that the simulator knows what input signals to simulate you need a so called tesbench.
10 10  
11 -A testbench lists the component you want to test e.g. abo. (You have written a vhdl file which behaves like ABO and this component is also called abo). And it instantiate this componant as a Unit Under Test (UUT). This component (uut) will be tested with the input and outputs you have specified later in a test process.
11 +A testbench lists the component you want to test e.g. abo. (You have written a vhdl file which behaves like ABO and this component is also called abo). It instantiate this componant as a Unit Under Test (UUT). This component (uut) will be tested with the input and outputs you have specified in a test process.
12 12  
13 -At first a testbench code example from ABO for better understanding.
13 +At first a testbench code example from ABO is shown for better understanding.
14 14  
15 15  {{code linenumbers="true"}}
16 -
17 17  --/*****************************************************************************/
18 18  --/* G E N E R A T E D V H D L C O D E */
19 19  --/*****************************************************************************/
... ... @@ -67,7 +67,6 @@
67 67  constant tick_period : time := 100 ns;
68 68  
69 69  BEGIN
70 -
71 71   uut: abo PORT MAP(
72 72   tick => tick,
73 73   reset => reset,
... ... @@ -81,7 +81,6 @@
81 81   B_out => B_out
82 82   );
83 83  
84 -
85 85   tick_process: process
86 86   begin
87 87   tick <= '0';
... ... @@ -90,7 +90,6 @@
90 90   wait for tick_period/2;
91 91   end process;
92 92  
93 -
94 94   -- Stimulus process
95 95   stim_proc: process
96 96   begin
... ... @@ -98,7 +98,6 @@
98 98  
99 99   --sim Process
100 100  
101 -
102 102   --NEW TRACE
103 103   reset <= '1';
104 104   wait for tick_period;
... ... @@ -216,12 +216,12 @@
216 216  Line 55: instantiation of uut
217 217  
218 218  (% style="margin-left: 30.0px;" %)
219 -Here ABO is instantiated
214 +Here is ABO instantiated
220 220  
221 221  Line 69: tick process
222 222  
223 223  (% style="margin-left: 30.0px;" %)
224 -The tick process simulates the tick. This signal is a kind of clock signal. Its cycle duration is set in variable tick_period.
219 +The tick process simulates the tick. This signal is a kind of a clock signal. Its cycle duration is set in variable tick_period.
225 225  
226 226  Line 79: the simulation process
227 227  
... ... @@ -233,14 +233,17 @@
233 233  
234 234  ----
235 235  
236 -Therefor the core ESO contains no information about input and output signals the proper SCL model is needed to generate the testbench.
231 +Therefore the core ESO contains no information about input and output signals the proper SCL model is needed to generate the testbench.
237 237  
238 -The variable declaration must fit to the used variables in the ESO file, logically.
233 +The variable declaration must conform to the used variables in the ESO file, logically.
239 239  
240 240  |=(((
241 241  SCL Model
242 242  )))|=(((
243 -Core ESO file
238 +Core ESO File
239 +)))|=(% colspan="1" %)(% colspan="1" %)
240 +(((
241 +ESO File
244 244  )))
245 245  |(((
246 246  {{code linenumbers="true" language="java"}}
... ... @@ -303,6 +303,25 @@
303 303  %% B_out : true
304 304  ;
305 305  {{/code}}
304 +)))|(% colspan="1" %)(% colspan="1" %)
305 +(((
306 +{{code linenumbers="true" language="perl"}}
307 +!reset ;
308 +A
309 +% Output : O1 A_out B_out
310 +;
311 +% Output : O1
312 +;
313 +B
314 +% Output : O2 B_out
315 +;
316 +!reset ;
317 +% Output :
318 +;
319 +A
320 +% Output : O2 A_out B_out
321 +;
322 +{{/code}}
306 306  )))
307 307  
308 308  {{note}}
... ... @@ -309,14 +309,101 @@
309 309  SCL file is not realy correct, will be corrected as soon as possible
310 310  {{/note}}
311 311  
312 -The lines 23 to 66 (testbench file) are generated from SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is loaded and the needed code is generated.
329 +The lines 23 to 66 (testbench file) were generated from the SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is needed for code generation.
313 313  
314 -The simulation process (starts at line 79) is genrates using the core ESO file.
315 -
316 316  
317 317  
333 +The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be shown at the following example:
334 +
335 +|=(% colspan="1" %)(% colspan="1" %)
336 +(((
337 +SCL
338 +)))|=(((
339 +ESO trace
340 +)))|=(% colspan="1" %)(% colspan="1" %)
341 +(((
342 +Testbench
343 +)))
344 +|(% colspan="1" %)(% colspan="1" %)
345 +(((
346 +{{code linenumbers="true" language="java"}}
347 +module test
348 +input A ;
349 +input B : boolean = false;
350 +input B_value : integer = 0;
351 +input C :boolean = false;
352 +input C_value :boolean = false;
353 +output D;
354 +output E : boolean = false;
355 +output E_value : integer = 5;
356 +output F : boolean = false;
357 +output F_value : boolean = false;
358 +{
359 + //pause;
360 +}
361 +{{/code}}
362 +)))|(((
363 +{{code linenumbers="true" language="perl"}}
364 +!reset;
365 +A C(false)
366 +%Output: D F(false)
367 +;
368 +{{/code}}
369 +
370 +normally the core ESO is used, but
371 +
372 + for better unterstanding we use the
373 +
374 + normal ESO trace
375 +
318 318  
377 +)))|(% colspan="1" %)(% colspan="1" %)
378 +(((
379 +{{code linenumbers="true" language="java"}}
380 +A <= true;
381 +B <= false;
382 +C <= true;
383 +C_value <= false;
384 +wait for tick_period;
385 +assert( D = true )
386 + report "1st trace: 1st tick: D should have been true"
387 + severity ERROR;
388 +assert( E = false )
389 + report "1st trace: 1st tick: E should have been false"
390 + severity ERROR;
391 +assert( F = true )
392 + report "1st trace: 1st tick: F should have been true"
393 + severity ERROR;
394 +assert( F_value = false )
395 + report "1st trace: 1st tick: F_value should have been false"
396 + severity ERROR;
397 +{{/code}}
398 +)))
319 319  
400 +**Set inputs**
401 +
402 +Line 2 and 3 in the testbench are setting the inputs. All (!) inputs must be set!
403 +
404 +* Pure signal which are present are set to the according value, e.g. //A<=true;//
405 +* Valued signals which are present are set to their according value e.g. //C_value <= false;// and set present //B<=true;//
406 +* ABSENT values (not listed in ESO files inputs) must be set absent
407 +** pure singals (not listed) e.g. K <= false
408 +** valued signals e.g. //B <= false//, only the present value will be set, the valued signal is not touched
409 +
410 +**Wait for the tick to pass by**
411 +
412 +The code //wait for tick_period;// waits for one tick, so the Hardware can compute the output values.
413 +
414 +**Test Outputs**
415 +
416 +After the tick has passed by we must check if the hardware computes the correct outputs. This is done by assertions. Every (!) output must be tested!
417 +
418 +* Pure signals: Test the pure output signal according to the current ESO tick, if listed in the tick, e.g. //assert( D = true )//. If it is not specified in the trace test for absence,
419 +* Valued signals: For valued signals, that are specified in the current ESO tick, test the present singal and the valued signal, e.g.// assert( F = true ) //and// assert( F_value = false)//
420 +* Valued signals, which are not listed in the current tick in the ESO file: test only the present flag for absence (We can say anything about absent valued signals)
421 +
422 +If an assertion failed the corresponding error will be printed to a log file. The severity level tells the simulator to go on with the simulation although an error occur.
423 +
320 320  
321 321  
322 322  
Confluence.Code.ConfluencePageClass[0]
Id
... ... @@ -1,1 +1,1 @@
1 -7111236
1 +7111275
URL
... ... @@ -1,1 +1,1 @@
1 -https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/KIELER/pages/7111236/ESO to VHDL Testbench
1 +https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/KIELER/pages/7111275/ESO to VHDL Testbench

Navigation

Quick Links

KIELER on GitHub
RTSYS Homepage