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1		-KIELER.SCCharts (DeprecatedHistorical Documentation & Features).The SC Language (SCL).Hardware Synthesis from SCCharts.WebHome
	1	+KIELER.SCCharts.SCCharts (DeprecatedHistorical Documentation).The SC Language (SCL).Hardware Synthesis from SCCharts.WebHome

Author

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1		-XWiki.stu230980
	1	+XWiki.gjo

Content

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322	322	{{/code}}
323	323	)))
324	324
325		-{{info}}
	325	+{{note}}
326	326	SCL file is not realy correct, will be corrected as soon as possible
327		-{{/info}}
	327	+{{/note}}
328	328
329	329	The lines 23 to 66 (testbench file) were generated from the SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is needed for code generation.
330	330
	331	+
331	331
332	332	The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be shown at the following example:
333	333
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378	378	C_value <= false;
379	379	wait for tick_period;
380	380	assert( D = true )
381		- report "1st trace: 1st tick: D should have been true"
382		- severity ERROR;
	382	+ report "1st trace: 1st tick: D should have been true"
	383	+ severity ERROR;
383	383	assert( E = false )
384		- report "1st trace: 1st tick: E should have been false"
385		- severity ERROR;
	385	+ report "1st trace: 1st tick: E should have been false"
	386	+ severity ERROR;
386	386	assert( F = true )
387		- report "1st trace: 1st tick: F should have been true"
388		- severity ERROR;
	388	+ report "1st trace: 1st tick: F should have been true"
	389	+ severity ERROR;
389	389	assert( F_value = false )
390		- report "1st trace: 1st tick: F_value should have been false"
391		- severity ERROR;
	391	+ report "1st trace: 1st tick: F_value should have been false"
	392	+ severity ERROR;
392	392	{{/code}}
393	393	)))
394	394
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411	411	After the tick has passed by we must check if the hardware computes the correct outputs. This is done by assertions. Every (!) output must be tested!
412	412
413	413	* Pure signals: Test the pure output signal according to the current ESO tick, if listed in the tick, e.g. //assert( D = true )//. If it is not specified in the trace test for absence,
414		-* Valued signals: For valued signals, that are specified in the current ESO tick, test the present singal and the valued signal, e.g.// assert( F = true ) //and// assert( F_value = false)//
	415	+* Valued signals: For valued signals, that are specified in the current ESO tick, test the present singal and the valued signal, e.g.// assert( F = true ) //and// assert( F_value = false)//
415	415	* Valued signals, which are not listed in the current tick in the ESO file: test only the present flag for absence (We can say anything about absent valued signals)
416	416
417	417	If an assertion failed the corresponding error will be printed to a log file. The severity level tells the simulator to go on with the simulation although an error occur.
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