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From version < 41.1 >
edited by cds
on 2014/12/09 11:16
To version < 47.1 >
edited by uru
on 2015/03/17 13:41
>
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1 -XWiki.cds
1 +XWiki.uru
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19 19  Our layout algorithm already supports the placement of edge labels. However, there's still room for improvement...
20 20  * **Layering Algorithms** (Bachelor, Master)
21 21  Implement an alternative algorithm for the layer assignment problem used in the layer-based approach to graph layout. The focus of the algorithm could the consideration of the number of edge crossings, a given aspect ratio, or overall compactness.
22 +* **Orthogonal "Edge Bundling"** (Bachelor, Master)
23 +Implement and evaluate strategies for orthogonal edge bundling within our layer-based layout algorithm.
22 22  * **Node Placement With a Focus on Compactness** (Master)
23 23  Node placement algorithms often try to draw as many edges as straight lines as possible. However, that usually results in less compact diagrams. The focus of this topic would be to devise or adapt a node placement algorithm that tries to strike a balance between straightness and compactness.
24 24  * **Compound Graph Layout** (Master)
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27 27  Develop methods for integrating port constraints in force-based drawing approaches. The resulting node placement shall be evaluated using an edge router such as [[libavoid>>url:http://www.adaptagrams.org/||shape="rect"]] on the model library of [[Ptolemy>>url:http://ptolemy.eecs.berkeley.edu/||shape="rect"]].
28 28  * **Combining Forces and Layers** (Master)**
29 29  **Design and implement a layout algorithm that combines the force-based and the layer-based approaches. The first three phases of the layer-based approach shall be replaced by a node distribution computed with a force-based approach.
32 +\\
30 30  
31 31  = Modeling Pragmatics =
32 32  
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41 41  
42 42  = Semantics and Synchronous Languages =
43 43  
44 -**Advisors:** Christian Motika, Steven Smyth.
47 +**Advisors:** Christian Motika, Steven Smyth
45 45  
46 -* **Validation Manager for Models**
49 +* **Automatic documentation generation for model-based languages **(Bachelor)
50 +Develop an automatic SCCharts documentation & comment system
51 +* **Merging SCCharts and KLOTS** (Bachelor)
52 +Implement KLOTS as demonstrator extension of the KIELER SCCharts implementation
53 +* **On the usability of the KIELER SCCharts compiler** (Bachelor)
54 +Evaluate the actual implementation of the KIELER SCCharts compiler and provide suggestions for improvements, i.e. the usability as standalone (commandline) compiler
55 +\\
56 +* **Validation Manager for Models **(Bachelor/Master)
47 47  Develop an integrated, flexible and generic syntactic validation framework for models (e.g. Esterel or SyncCharts).
48 -* **SCCharts compiler validation with Esterel**
58 +* **SCCharts compiler validation with Esterel **(Bachelor/Master)
49 49  Automate the validation of the SCCharts compiler using the Esterel simulation.
50 -* **Transformation from SCCharts to Esterel** [possibly also Master Topic]
60 +* **Transformation from SCCharts to Esterel** (Bachelor/Master)
51 51  Develop a transformation in Xtend2 to generate Esterel code for SCCharts.
52 -* **Hardware Synthesis from SCCharts to FPGA **[possibly also Master Topic]
53 -Use the circuit-based code generation to produce code for FPGAs
54 -* **Automatic documentation generation **[possibly also Master Topic]
55 -Develop an automatic SCCharts documentation system
56 -* **Optimizations for the SCCharts compiler **[possibly also Master Topic]
57 -Profile the actual SCCharts compiler and apply optimizations
58 -* **Multi-core SCCharts compiler **[possibly also Master Topic]
59 -Implement the possibility to use more than one core to compile large SCCharts
60 -* **Adding dataflow to SCCharts** [possibly also Master Topic]
61 -Add dataflow to SCCharts
62 +* **Hardware Synthesis from SCCharts to FPGA **(Bachelor/Master)
63 +Use the circuit-based code generation approach to produce code for FPGAs
64 +* (% style="line-height: 1.4285715;" %)**Optimization of the SCCharts compiler **(%%)(Bachelor/Master)
65 +Profile the actual SCCharts compiler and apply optimizations; also evaluate the possibility to use multiple cores for compilation
66 +* **Optimization of the SCCharts transformations** (Bachelor/Master)
67 +Profile the actual SCCharts transformations and apply optimizations
68 +* **SCCharts Andriod backend for Mini Drones** (Bachelor/Master)  [work in progress, Bachelor/Master project summer term 2015]
69 +Develop a new code generation backend for SCCharts for Andriod applications with Mini Drones as demonstrator
70 +* **On the pragmatics of modelling large models in SCCharts** (Bachelor/Master)
71 +Evaluate the possibilities to create and maintain large models in model-based languages (i.e. SCCharts) and provide suggestions for improvements
72 +* **Extend the SC MoC to handle priority-based variable accesses** (Bachelor/Master)
73 +Add priorities to variable accesses to extend the SC MoC and therefore the number of valid sequentially constructive synchronous programs.
74 +\\
75 +* **Detecting tick boundaries in SCCharts **(Master/Bachelor)
76 +Implement an algorithm that detects tick boundaries (in concurrent) threads and therefore improves the scheduling
77 +* **Efficient data dependency analyses in SCCharts** (Master/Bachelor)
78 +Implement data dependency analyses for SCCharts to improve static scheduling of the compiler
79 +* **KIELER evaluation environment for synchronous languages** (Master/Bachelor)
80 +Develop a reliable evaluation environment to compare common synchronous languages (i.e. Esterel/SyncCharts & SCCharts)
81 +* **Raceyard evaluation** (Master/Bachelor)
82 +Evaluate the possibility for the use of SCCharts in the Raceyard context and pave the way for future experiments
83 +\\
84 +* **Quartz **(Master)
85 +Integrate the synchronous Quartz language into KIELER for validation purposes and teaching.
86 +* **Implementation of a priority-based compilation approach **(Master) [work in progress, Caroline Butschek]
87 +Implement the SyncCharts priority-based compilation approach into the SCCharts compiler chain.
88 +* **From Esterel to SCL **(Master) [work in progress, Karsten Rathlev]
89 +Implement transformations that translate Esterel programs to SCL
90 +* **Curing Schizophrenia in SCCharts **(Master)
91 +Develop new synchronizer to handle schizophrenia properly (e.g. depth join).**
92 +**
93 +* **Railway 4.0 **(Master) [work in progress, Nis Wechselberg]
94 +Design a new and modern hardware controlling (Version 4) for the railway installation.
62 62  
63 63  = PRETSY / PRETSY2 =
64 64  
65 -**Advisors:** Insa Fuhrmann.
98 +**Advisors:** Insa Fuhrmann, Steven Smyth
66 66  
67 -* **Real-time extensions for SCCharts** [possibly also Master Topic]
100 +* **Real-time extensions for SCCharts** (Bachelor/Master)
68 68  Make the timing instructions //delay_until// und //exception_on_expire// of the [[FlexPRET>>url:http://rtsys.informatik.uni-kiel.de/confluence/Multithreaded/Multicore execution of SCCharts Evaluate possibilities to preserve parallelism in SCCharts, implement mapping for (fine grained) multithreading and multicore based on the FlexPRET||shape="rect"]] processor available in SCCharts.
69 -* See also Semantics and Synchronous Languages: **Adding dataflow to SCCharts**
102 +* **Adding dataflow to SCCharts** (Bachelor/Master) [work in progress, Axel Umland]
103 +Add dataflow to SCCharts 
104 +\\
105 +* **Multithreaded/Multicore execution of SCCharts **(Master/Bachelor)  [work in progress, Tibor Weiß]
106 +Evaluate possibilities to preserve parallelism in SCCharts, implement mapping for (fine grained) multithreading and multicore 
107 +based on the [[FlexPRET>>url:http://www.eecs.berkeley.edu/Pubs/TechRpts/2013/EECS-2013-172.pdf||shape="rect"]] processor.
70 70  
71 -= Miscellaneous Topics =
109 += (% style="color: rgb(0,0,0);" %)Miscellaneous Topics(%%) =
72 72  
73 73  **Advisors:** to be determined.
74 74  
75 75  * **Developing an Info Screen** (Bachelor)
76 76  Info screens are screens that present data in ways that can be easily understood. This includes static data (project description graphics, members of a team, ...) as well as dynamically aggregated data (bug statistics, automatic build overviews, ...). This topic is about developing such an info screen for our group and making it easily configurable.
77 -
78 -----
79 -
80 -= (% style="color: rgb(0,0,0);" %)Master Topics(%%) =
81 -
82 -== Semantics and Synchronous Languages ==
83 -
84 -* **Quartz**
85 -Integrate the synchronous Quartz language into KIELER for validation purposes and teaching.
86 -* **Implementation of a priority-based compilation approach**
87 -Implement the SyncCharts priority-based compilation approach into the SCCharts compiler chain.
88 -* **Curing Schizophrenia in SCCharts**
89 -Develop new synchronizer to handle schizophrenia properly (e.g. depth join).
90 -* **Detecting tick boundaries in SCCharts**
91 -Implement an algorithm that detects tick boundaries (in concurrent) threads and therefore improves the scheduling
92 -* **Multithreaded/Multicore execution of SCCharts **(see below PRETSY/PRETSY2)**
93 -**
94 -* **Railway 2.0**
95 -Design a new and modern hardware controlling (Version 4) for the railway installation.
96 -
97 -== PRETSY / PRETSY2 ==
98 -
99 -* **Multithreaded/Multicore execution of SCCharts**
100 -Evaluate possibilities to preserve parallelism in SCCharts, implement mapping for (fine grained) multithreading and multicore
101 -based on the [[FlexPRET>>url:http://www.eecs.berkeley.edu/Pubs/TechRpts/2013/EECS-2013-172.pdf||shape="rect"]] processor.**
102 -**
103 -
104 -
Confluence.Code.ConfluencePageClass[0]
Id
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1 -10748078
1 +10751491
URL
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1 -https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/RTSYS/pages/10748078/Topics for Student Theses
1 +https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/RTSYS/pages/10751491/Topics for Student Theses