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30	30	Automate the validation of the SCCharts compiler using the Esterel simulation.
31	31	* **Transformation from SCCharts to Esterel** [possibly also Master Topic]
32	32	Develop a transformation in Xtend2 to generate Esterel code for SCCharts.
33		-* **Hardware Synthesis from SCCharts to FPGA**
34		-* **Automatic documentation generation out of annotations **[possibly also Master Topic]
35		-* **Optimizations for the SCCharts compiler**
	33	+* **Hardware Synthesis from SCCharts to FPGA **[possibly also Master Topic]
	34	+Use the circuit-based code generation to produce code for FPGAs
	35	+* **Automatic documentation generation **[possibly also Master Topic]
	36	+Develop an automatic SCCharts documentation system
	37	+* **Optimizations for the SCCharts compiler **[possibly also Master Topic]
	38	+Profile the actual SCCharts compiler and apply optimizations
	39	+* **Multi-core SCCharts compiler **[possibly also Master Topic]
	40	+Implement the possibility to use more than one core to compile large SCCharts
	41	+* **Adding dataflow to SCCharts** [possibly also Master Topic]
	42	+Add dataflow to SCCharts
36	36
37	37	== Miscellaneous Topics ==
38	38
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68	68	* **Quartz**
69	69	Integrate the synchronous Quartz language into KIELER for validation purposes and teaching.
70	70	* **Implementation of a priority-based compilation approach**
71		-* **Curing Schizophrenia with Depth Join**
72		-* **Adding dataflow to SCCharts**
	78	+Implement the SyncCharts priority-based compilation approach into the SCCharts compiler chain.
	79	+* **Curing Schizophrenia in SCCharts**
	80	+Develop new synchronizer to handle schizophrenia properly (e.g. depth join).
73	73	* **Detecting tick boundaries in SCCharts**
74		-* **Preserving concurrency for multi-core **
	82	+Implement an algorithm that detects tick boundaries (in concurrent) threads and therefore improves the scheduling
	83	+* **Preserving concurrency/parallelism for multi-core **
	84	+Evaluate possibilities to preserve parallelism in SCCharts**.
	85	+**
75	75	* **Railway 2.0**
	87	+Design a new and modern hardware controlling (Version 4) for the railway installation.

Confluence.Code.ConfluencePageClass[0]

Id

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1		-9471792
	1	+9471821

URL

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1		-https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/RTSYS/pages/9471792/Topics for Student Theses
	1	+https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/RTSYS/pages/9471821/Topics for Student Theses