Summary

• Page properties (2 modified, 0 added, 0 removed)
• Objects (1 modified, 0 added, 0 removed)
  • Confluence.Code.ConfluencePageClass[0]

Details

Page properties

Author

...	...	@@ -1,1 +1,1 @@
1		-XWiki.uru
	1	+XWiki.cds

Content

...	...	@@ -1,5 +1,11 @@
1		-Here's a selection of possible bachelor and master topics. If you're interested in one of them, don't hesitate to contact us! We'll sit down, have tea, and talk about what we could do together.
	1	+Here's a selection of possible bachelor and master topics. If you're interested in one of them, don't hesitate to contact us! We'll sit down, have tea, and talk about what we great things we could do together.
2	2
	3	+**On this Page**
	4	+
	5	+
	6	+
	7	+{{toc/}}
	8	+
3	3	= Bachelor Topics =
4	4
5	5	== Graph Layout ==
...	...	@@ -8,7 +8,9 @@
8	8	The order of nodes in a layer determines the number of crossings and is computed during the crossing minimization step. The results can usually be further improved by switching the order of nodes around, which we currently lack proper algorithms for.
9	9	* **{{jira columns="key,summary,type,created,updated,due,assignee,reporter,priority,status,resolution" id="KIELER JIRA" serverId="2851bd34-0bf1-3f02-ab12-7d77ccab0fae" key="KIPRA-891"}}KIPRA-891{{/jira}}Layering Algorithms**
10	10	Implement an alternative algorithm for the layer assignment problem used in the layer-based approach to graph layout.
11		-* **Integrate KIML with JGraph**
	17	+* Tight Packing of Connected Components
	18	+Different connected components of a graph are often laid out separately and combined again afterwards. This combination step often produces too much whitespace. Research relevant 2D packing literature and implement a better solution.
	19	+* **{{jira columns="key,summary,type,created,updated,due,assignee,reporter,priority,status,resolution" id="KIELER JIRA" serverId="2851bd34-0bf1-3f02-ab12-7d77ccab0fae" jqlQuery="key in (KIPRA-1262,KIPRA-1031)" source="jql" maximumIssues="20"}}key in (KIPRA-1262,KIPRA-1031){{/jira}}Integrate KIML with JGraph**
12	12	Provide automatic layout through KIML for the JGraph diagram library and develop a simple JGraph-based graph editor to test the integration with.
13	13	* **{{jira showSummary="true" columns="key,summary,type,created,updated,due,assignee,reporter,priority,status,resolution" id="KIELER JIRA" serverId="2851bd34-0bf1-3f02-ab12-7d77ccab0fae" key="KIPRA-1214"}}KIPRA-1214{{/jira}}Improved Edge Label Placement**
14	14	Our layout algorithm already supports the placement of edge labels. However, there's still room for improvement...
...	...	@@ -15,6 +15,8 @@
15	15
16	16	== Modeling Pragmatics ==
17	17
	26	+* **Comment Attachment**
	27	+When computing a new layout for a diagram that contains comments (comparable to comments in source code), the comments often get placed far away of the nodes they refer to. This is because often the reference is not explicitly encoded in the original model. We have used a distance-based metric in the past to discover references automatically, but there are lots of ideas for improvement. This bachelor thesis would implement them, perhaps come up with additional ideas, and finally evaluate them in a thorough experiment.
18	18	* **Control Flow Graph Exploration / Visualization**
19	19	Use pragmatics concepts (automatic layout, focus & context) for exploring/visualizing control flow graphs and specific paths, eg. as computed by OTAWA WCET analysis tool, eg. using Klighd.
20	20	* **OMG DD Format**
...	...	@@ -24,10 +24,20 @@
24	24
25	25	* **Validation Manager for Models**
26	26	Develop an integrated, flexible and generic syntactic validation framework for models (e.g. Esterel or SyncCharts).
27		-* **Esterel / SyncCharts Validation**
28		-Automate the validation for a (generic) SyncCharts simulator employing the Esterel simulator and the Esterel to SyncCharts transformation.
29		-* **Transformation from SyncCharts to Esterel** [possibly also Master Topic]
30		-Develop a transformation in Xtend2 to generate Esterel code for SyncCharts.
	37	+* **SCCharts compiler validation with Esterel**
	38	+Automate the validation of the SCCharts compiler using the Esterel simulation.
	39	+* **Transformation from SCCharts to Esterel** [possibly also Master Topic]
	40	+Develop a transformation in Xtend2 to generate Esterel code for SCCharts.
	41	+* **Hardware Synthesis from SCCharts to FPGA **[possibly also Master Topic]
	42	+Use the circuit-based code generation to produce code for FPGAs
	43	+* **Automatic documentation generation **[possibly also Master Topic]
	44	+Develop an automatic SCCharts documentation system
	45	+* **Optimizations for the SCCharts compiler **[possibly also Master Topic]
	46	+Profile the actual SCCharts compiler and apply optimizations
	47	+* **Multi-core SCCharts compiler **[possibly also Master Topic]
	48	+Implement the possibility to use more than one core to compile large SCCharts
	49	+* **Adding dataflow to SCCharts** [possibly also Master Topic]
	50	+Add dataflow to SCCharts
31	31
32	32	== Miscellaneous Topics ==
33	33
...	...	@@ -58,7 +58,16 @@
58	58
59	59	== Semantics and Synchronous Languages ==
60	60
61		-* **FPGA Statecharts**
62		-Development of a Statecharts editor, based on .NET, WPF, MS Silverlight. Synthesis onto FPGAs with a data-flow-based intermediate format.
63		-* **[Quartz]**
	81	+* **Quartz**
64	64	Integrate the synchronous Quartz language into KIELER for validation purposes and teaching.
	83	+* **Implementation of a priority-based compilation approach**
	84	+Implement the SyncCharts priority-based compilation approach into the SCCharts compiler chain.
	85	+* **Curing Schizophrenia in SCCharts**
	86	+Develop new synchronizer to handle schizophrenia properly (e.g. depth join).
	87	+* **Detecting tick boundaries in SCCharts**
	88	+Implement an algorithm that detects tick boundaries (in concurrent) threads and therefore improves the scheduling
	89	+* **Preserving concurrency/parallelism for multi-core **
	90	+Evaluate possibilities to preserve parallelism in SCCharts**.
	91	+**
	92	+* **Railway 2.0**
	93	+Design a new and modern hardware controlling (Version 4) for the railway installation.

Confluence.Code.ConfluencePageClass[0]

Id

...	...	@@ -1,1 +1,1 @@
1		-9471600
	1	+9471823

URL

...	...	@@ -1,1 +1,1 @@
1		-https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/RTSYS/pages/9471600/Topics for Student Theses
	1	+https://rtsys.informatik.uni-kiel.de/confluence//wiki/spaces/RTSYS/pages/9471823/Topics for Student Theses