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75 75  (% style="color:#333333" %)F. G. R. de Souza, J. de Melo Bezerra, C. M. Hirata, P. de Saqui-Sannes and L. Apvrille, [[Combining STPA with SysML Modeling>>url:https://ieeexplore.ieee.org/document/9275867||shape="rect"]]. //2020 IEEE International Systems Conference (SysCon)//, 2020, pp. 1-8, doi: 10.1109/SysCon47679.2020.9275867.
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78 -J. Kloos, T. Hussain, and R. Eschbach. [[Risk-based testing of safety-critical embedded systems driven by fault tree analysis>>url:https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5954386]]. In //2011 IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops//, pp. 26-33. IEEE, 2011.
78 +**[assigned]** J. Kloos, T. Hussain, and R. Eschbach. [[Risk-based testing of safety-critical embedded systems driven by fault tree analysis>>url:https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5954386]]. In //2011 IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops//, pp. 26-33. IEEE, 2011.
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81 81  L. A. Cortes, P. Eles and Z. Peng, [[Formal coverification of embedded systems using model checking>>url:https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=874622&tag=1]]. //Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future//. Vol. 1. IEEE, 2000.