----------------------------------------------------------------------------------
-- Company:       Uni Kiel - RTsys
-- Engineer:      Gunnar Johannsen (gjo)
-- 
-- Create Date:    10:45:08 05/09/2013 
-- Design Name: 
-- Module Name:    Main_Abo - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: ABO_seq.c direct implemented into a process. No other changes
--              were made. No external FF or initial tick generation, why: see below.
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Main_Abo is
    Port ( tick : in  STD_LOGIC;
           A_in : in  boolean;
           B_in : in  boolean;
           O1 : out  boolean;
           O2 : out  boolean;
           A_out : out  boolean;
           B_out : out  boolean
           );
end Main_Abo;

architecture Behavioral of Main_Abo is

component abo_seq is
    Port ( A_in : in  boolean;
           B_in : in  boolean;
           O1 : out  boolean;
           O2 : out  boolean;
           A_out : out  boolean;
           B_out : out  boolean;
           --
           tick : in STD_LOGIC);
 --          entry : in boolean);
end component;

   signal A_in_int : boolean := false;
   signal B_in_int : boolean := false;
   signal O1_int : boolean := false;
   signal O2_int : boolean := false;
   signal A_out_int : boolean := false;
   signal B_out_int : boolean := false;
--   signal entry_int : boolean := false;

--   signal u_notInitial : boolean := false;
--   signal u_notInitialDetect : boolean:= true;

begin

abo : abo_seq port map(
      A_in => A_in_int,
      B_in => B_in_int,
      O1 => O1_int,
      O2 => O2_int,
      A_out => A_out_int,
      B_out => B_out_int,
           
      tick => tick
 --     entry => entry_int
   );
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- This input FF could not be used, because this inner Abo-seq component has 
-- output FF too. If eg. Input A is present, the output from A will be one 
-- cycle later present (because of output FF). Thats not what we want.

--   abo_proc : process
--   begin
--      wait until rising_edge(tick);
--      A_in_int <= A_in;
--      B_in_int <= B_in; 
--      
--   end process;
   
   A_in_int <= A_in;
   B_in_int <= B_in; 
   
   O1 <= O1_int;
   O2 <= O2_int;
   A_out <= A_out_int;
   B_out <= B_out_int;

-- ----------------------------------------------------------------------------
-- The outside initial tick process could not be used here,
-- because the initial tick value will be transfered via a signal
-- to the inner component. A signal value is valid in the next clk (tick) cycle.
-- So the initial tick will arrive one tick to later as it should...

--   initialTick: process
----      variable u_notInitial : boolean := false;
----      variable u_notInitialDetect : boolean:= true;
--      variable u_entry : boolean;
--      
--      begin
--         wait until rising_edge(tick);
--         
--         u_entry := not u_notInitial;
--         
--        if ( not (u_notInitial = true)) then
--          u_notInitial := u_notInitialDetect;
--        end if;
--         
----         entry_int <= u_entry;
--   end process;

-- ----------------------------------------------------------------------------

end Behavioral;

