scchart rail {
  input bool second;
  bool IC_JCT_0_T1 = false;
  bool IC_LN_0_T1 = false;
  bool IC_LN_1_T1 = false;
  bool IC_LN_2_T1 = false;
  bool IC_LN_3_T1 = false;
  bool IC_LN_4_T1 = false;
  bool IC_LN_5_T1 = false;
  bool IC_ST_0_T1 = false;
  bool IC_ST_1_T1 = false;
  bool IC_ST_2_T1 = false;
  bool IC_ST_3_T1 = false;
  bool IC_ST_4_T1 = false;
  bool IO_LN_0_T1 = false;
  bool IO_LN_1_T1 = false;
  bool IO_LN_2_T1 = false;
  bool KH_LN_0_T1 = false;
  bool KH_LN_1_T1 = false;
  bool KH_LN_2_T1 = false;
  bool KH_LN_3_T1 = false;
  bool KH_LN_4_T1 = false;
  bool KH_LN_5_T1 = false;
  bool KH_LN_6_T1 = false;
  bool KH_LN_7_T1 = false;
  bool KH_LN_8_T1 = false;
  bool KH_ST_0_T1 = false;
  bool KH_ST_1_T1 = false;
  bool KH_ST_2_T1 = false;
  bool KH_ST_3_T1 = false;
  bool KH_ST_4_T1 = false;
  bool KH_ST_5_T1 = false;
  bool KH_ST_6_T1 = false;
  bool KIO_LN_0_T1 = false;
  bool KIO_LN_1_T1 = false;
  bool OC_JCT_0_T1 = false;
  bool OC_LN_0_T1 = false;
  bool OC_LN_1_T1 = false;
  bool OC_LN_2_T1 = false;
  bool OC_LN_3_T1 = false;
  bool OC_LN_4_T1 = false;
  bool OC_LN_5_T1 = false;
  bool OC_ST_0_T1 = false;
  bool OC_ST_1_T1 = false;
  bool OC_ST_2_T1 = false;
  bool OC_ST_3_T1 = false;
  bool OC_ST_4_T1 = false;
  bool OI_LN_0_T1 = false;
  bool OI_LN_1_T1 = false;
  bool OI_LN_2_T1 = false;
  bool IC_JCT_0_T2 = false;
  bool IC_LN_0_T2 = false;
  bool IC_LN_1_T2 = false;
  bool IC_LN_2_T2 = false;
  bool IC_LN_3_T2 = false;
  bool IC_LN_4_T2 = false;
  bool IC_LN_5_T2 = false;
  bool IC_ST_0_T2 = false;
  bool IC_ST_1_T2 = false;
  bool IC_ST_2_T2 = false;
  bool IC_ST_3_T2 = false;
  bool IC_ST_4_T2 = false;
  bool IO_LN_0_T2 = false;
  bool IO_LN_1_T2 = false;
  bool IO_LN_2_T2 = false;
  bool KH_LN_0_T2 = false;
  bool KH_LN_1_T2 = false;
  bool KH_LN_2_T2 = false;
  bool KH_LN_3_T2 = false;
  bool KH_LN_4_T2 = false;
  bool KH_LN_5_T2 = false;
  bool KH_LN_6_T2 = false;
  bool KH_LN_7_T2 = false;
  bool KH_LN_8_T2 = false;
  bool KH_ST_0_T2 = false;
  bool KH_ST_1_T2 = false;
  bool KH_ST_2_T2 = false;
  bool KH_ST_3_T2 = false;
  bool KH_ST_4_T2 = false;
  bool KH_ST_5_T2 = false;
  bool KH_ST_6_T2 = false;
  bool KIO_LN_0_T2 = false;
  bool KIO_LN_1_T2 = false;
  bool OC_JCT_0_T2 = false;
  bool OC_LN_0_T2 = false;
  bool OC_LN_1_T2 = false;
  bool OC_LN_2_T2 = false;
  bool OC_LN_3_T2 = false;
  bool OC_LN_4_T2 = false;
  bool OC_LN_5_T2 = false;
  bool OC_ST_0_T2 = false;
  bool OC_ST_1_T2 = false;
  bool OC_ST_2_T2 = false;
  bool OC_ST_3_T2 = false;
  bool OC_ST_4_T2 = false;
  bool OI_LN_0_T2 = false;
  bool OI_LN_1_T2 = false;
  bool OI_LN_2_T2 = false;
  int IC_JCT_0_perm = -1;
  int IC_LN_0_perm = -1;
  int IC_LN_1_perm = -1;
  int IC_LN_2_perm = -1;
  int IC_LN_3_perm = -1;
  int IC_LN_4_perm = -1;
  int IC_LN_5_perm = -1;
  int IC_ST_0_perm = -1;
  int IC_ST_1_perm = -1;
  int IC_ST_2_perm = 1;
  int IC_ST_3_perm = -1;
  int IC_ST_4_perm = -1;
  int IO_LN_0_perm = -1;
  int IO_LN_1_perm = -1;
  int IO_LN_2_perm = -1;
  int KH_LN_0_perm = -1;
  int KH_LN_1_perm = -1;
  int KH_LN_2_perm = -1;
  int KH_LN_3_perm = -1;
  int KH_LN_4_perm = -1;
  int KH_LN_5_perm = -1;
  int KH_LN_6_perm = -1;
  int KH_LN_7_perm = -1;
  int KH_LN_8_perm = -1;
  int KH_ST_0_perm = -1;
  int KH_ST_1_perm = -1;
  int KH_ST_2_perm = -1;
  int KH_ST_3_perm = -1;
  int KH_ST_4_perm = -1;
  int KH_ST_5_perm = -1;
  int KH_ST_6_perm = -1;
  int KIO_LN_0_perm = -1;
  int KIO_LN_1_perm = -1;
  int OC_JCT_0_perm = -1;
  int OC_LN_0_perm = -1;
  int OC_LN_1_perm = -1;
  int OC_LN_2_perm = -1;
  int OC_LN_3_perm = -1;
  int OC_LN_4_perm = -1;
  int OC_LN_5_perm = -1;
  int OC_ST_0_perm = -1;
  int OC_ST_1_perm = -1;
  int OC_ST_2_perm = -1;
  int OC_ST_3_perm = -1;
  int OC_ST_4_perm = -1;
  int OI_LN_0_perm = -1;
  int OI_LN_1_perm = -1;
  int OI_LN_2_perm = -1;

  initial state station_ctrl "station controller" {

    region controller:

    initial state tick
    --> T1;

    state T1 {
      entry IC_JCT_0_T1 && IC_JCT_0_perm == -1 / IC_JCT_0_perm = 1;
      entry IC_JCT_0_T1 && IC_JCT_0_perm == 0 / IC_JCT_0_perm = 1;
      entry !IC_JCT_0_T1 && IC_JCT_0_perm == 1 / IC_JCT_0_perm = 0;
      entry IC_LN_0_T1 && IC_LN_0_perm == 0 / IC_LN_0_perm = 1;
      entry !IC_LN_0_T1 && IC_LN_0_perm == 1 / IC_LN_0_perm = 0;
      entry IC_LN_1_T1 && IC_LN_1_perm == 0 / IC_LN_1_perm = 1;
      entry !IC_LN_1_T1 && IC_LN_1_perm == 1 / IC_LN_1_perm = 0;
      entry IC_LN_2_T1 && IC_LN_2_perm == 0 / IC_LN_2_perm = 1;
      entry !IC_LN_2_T1 && IC_LN_2_perm == 1 / IC_LN_2_perm = 0;
      entry IC_LN_3_T1 && IC_LN_3_perm == 0 / IC_LN_3_perm = 1;
      entry !IC_LN_3_T1 && IC_LN_3_perm == 1 / IC_LN_3_perm = 0;
      entry IC_LN_4_T1 && IC_LN_4_perm == 0 / IC_LN_4_perm = 1;
      entry !IC_LN_4_T1 && IC_LN_4_perm == 1 / IC_LN_4_perm = 0;
      entry IC_LN_5_T1 && IC_LN_5_perm == 0 / IC_LN_5_perm = 1;
      entry !IC_LN_5_T1 && IC_LN_5_perm == 1 / IC_LN_5_perm = 0;
      entry IC_ST_0_T1 && IC_ST_0_perm == 0 / IC_ST_0_perm = 1;
      entry !IC_ST_0_T1 && IC_ST_0_perm == 1 / IC_ST_0_perm = 0;
      entry IC_ST_1_T1 && IC_ST_1_perm == 0 / IC_ST_1_perm = 1;
      entry !IC_ST_1_T1 && IC_ST_1_perm == 1 / IC_ST_1_perm = 0;
      entry IC_ST_2_T1 && IC_ST_2_perm == 0 / IC_ST_2_perm = 1;
      entry !IC_ST_2_T1 && IC_ST_2_perm == 1 / IC_ST_2_perm = 0;
      entry IC_ST_3_T1 && IC_ST_3_perm == 0 / IC_ST_3_perm = 1;
      entry !IC_ST_3_T1 && IC_ST_3_perm == 1 / IC_ST_3_perm = 0;
      entry IC_ST_4_T1 && IC_ST_4_perm == 0 / IC_ST_4_perm = 1;
      entry !IC_ST_4_T1 && IC_ST_4_perm == 1 / IC_ST_4_perm = 0;
      entry IO_LN_0_T1 && IO_LN_0_perm == 0 / IO_LN_0_perm = 1;
      entry !IO_LN_0_T1 && IO_LN_0_perm == 1 / IO_LN_0_perm = 0;
      entry IO_LN_1_T1 && IO_LN_1_perm == 0 / IO_LN_1_perm = 1;
      entry !IO_LN_1_T1 && IO_LN_1_perm == 1 / IO_LN_1_perm = 0;
      entry IO_LN_2_T1 && IO_LN_2_perm == 0 / IO_LN_2_perm = 1;
      entry !IO_LN_2_T1 && IO_LN_2_perm == 1 / IO_LN_2_perm = 0;
      entry KH_LN_0_T1 && KH_LN_0_perm == 0 / KH_LN_0_perm = 1;
      entry !KH_LN_0_T1 && KH_LN_0_perm == 1 / KH_LN_0_perm = 0;
      entry KH_LN_1_T1 && KH_LN_1_perm == 0 / KH_LN_1_perm = 1;
      entry !KH_LN_1_T1 && KH_LN_1_perm == 1 / KH_LN_1_perm = 0;
      entry KH_LN_2_T1 && KH_LN_2_perm == 0 / KH_LN_2_perm = 1;
      entry !KH_LN_2_T1 && KH_LN_2_perm == 1 / KH_LN_2_perm = 0;
      entry KH_LN_3_T1 && KH_LN_3_perm == 0 / KH_LN_3_perm = 1;
      entry !KH_LN_3_T1 && KH_LN_3_perm == 1 / KH_LN_3_perm = 0;
      entry KH_LN_4_T1 && KH_LN_4_perm == 0 / KH_LN_4_perm = 1;
      entry !KH_LN_4_T1 && KH_LN_4_perm == 1 / KH_LN_4_perm = 0;
      entry KH_LN_5_T1 && KH_LN_5_perm == 0 / KH_LN_5_perm = 1;
      entry !KH_LN_5_T1 && KH_LN_5_perm == 1 / KH_LN_5_perm = 0;
      entry KH_LN_6_T1 && KH_LN_6_perm == 0 / KH_LN_6_perm = 1;
      entry !KH_LN_6_T1 && KH_LN_6_perm == 1 / KH_LN_6_perm = 0;
      entry KH_LN_7_T1 && KH_LN_7_perm == 0 / KH_LN_7_perm = 1;
      entry !KH_LN_7_T1 && KH_LN_7_perm == 1 / KH_LN_7_perm = 0;
      entry KH_LN_8_T1 && KH_LN_8_perm == 0 / KH_LN_8_perm = 1;
      entry !KH_LN_8_T1 && KH_LN_8_perm == 1 / KH_LN_8_perm = 0;
      entry KH_ST_0_T1 && KH_ST_0_perm == 0 / KH_ST_0_perm = 1;
      entry !KH_ST_0_T1 && KH_ST_0_perm == 1 / KH_ST_0_perm = 0;
      entry KH_ST_1_T1 && KH_ST_1_perm == 0 / KH_ST_1_perm = 1;
      entry !KH_ST_1_T1 && KH_ST_1_perm == 1 / KH_ST_1_perm = 0;
      entry KH_ST_2_T1 && KH_ST_2_perm == 0 / KH_ST_2_perm = 1;
      entry !KH_ST_2_T1 && KH_ST_2_perm == 1 / KH_ST_2_perm = 0;
      entry KH_ST_3_T1 && KH_ST_3_perm == 0 / KH_ST_3_perm = 1;
      entry !KH_ST_3_T1 && KH_ST_3_perm == 1 / KH_ST_3_perm = 0;
      entry KH_ST_4_T1 && KH_ST_4_perm == 0 / KH_ST_4_perm = 1;
      entry !KH_ST_4_T1 && KH_ST_4_perm == 1 / KH_ST_4_perm = 0;
      entry KH_ST_5_T1 && KH_ST_5_perm == 0 / KH_ST_5_perm = 1;
      entry !KH_ST_5_T1 && KH_ST_5_perm == 1 / KH_ST_5_perm = 0;
      entry KH_ST_6_T1 && KH_ST_6_perm == 0 / KH_ST_6_perm = 1;
      entry !KH_ST_6_T1 && KH_ST_6_perm == 1 / KH_ST_6_perm = 0;
      entry KIO_LN_0_T1 && KIO_LN_0_perm == 0 / KIO_LN_0_perm = 1;
      entry !KIO_LN_0_T1 && KIO_LN_0_perm == 1 / KIO_LN_0_perm = 0;
      entry KIO_LN_1_T1 && KIO_LN_1_perm == 0 / KIO_LN_1_perm = 1;
      entry !KIO_LN_1_T1 && KIO_LN_1_perm == 1 / KIO_LN_1_perm = 0;
      entry OC_JCT_0_T1 && OC_JCT_0_perm == 0 / OC_JCT_0_perm = 1;
      entry !OC_JCT_0_T1 && OC_JCT_0_perm == 1 / OC_JCT_0_perm = 0;
      entry OC_LN_0_T1 && OC_LN_0_perm == 0 / OC_LN_0_perm = 1;
      entry !OC_LN_0_T1 && OC_LN_0_perm == 1 / OC_LN_0_perm = 0;
      entry OC_LN_1_T1 && OC_LN_1_perm == 0 / OC_LN_1_perm = 1;
      entry !OC_LN_1_T1 && OC_LN_1_perm == 1 / OC_LN_1_perm = 0;
      entry OC_LN_2_T1 && OC_LN_2_perm == 0 / OC_LN_2_perm = 1;
      entry !OC_LN_2_T1 && OC_LN_2_perm == 1 / OC_LN_2_perm = 0;
      entry OC_LN_3_T1 && OC_LN_3_perm == 0 / OC_LN_3_perm = 1;
      entry !OC_LN_3_T1 && OC_LN_3_perm == 1 / OC_LN_3_perm = 0;
      entry OC_LN_4_T1 && OC_LN_4_perm == 0 / OC_LN_4_perm = 1;
      entry !OC_LN_4_T1 && OC_LN_4_perm == 1 / OC_LN_4_perm = 0;
      entry OC_LN_5_T1 && OC_LN_5_perm == 0 / OC_LN_5_perm = 1;
      entry !OC_LN_5_T1 && OC_LN_5_perm == 1 / OC_LN_5_perm = 0;
      entry OC_ST_0_T1 && OC_ST_0_perm == 0 / OC_ST_0_perm = 1;
      entry !OC_ST_0_T1 && OC_ST_0_perm == 1 / OC_ST_0_perm = 0;
      entry OC_ST_1_T1 && OC_ST_1_perm == 0 / OC_ST_1_perm = 1;
      entry !OC_ST_1_T1 && OC_ST_1_perm == 1 / OC_ST_1_perm = 0;
      entry OC_ST_2_T1 && OC_ST_2_perm == 0 / OC_ST_2_perm = 1;
      entry !OC_ST_2_T1 && OC_ST_2_perm == 1 / OC_ST_2_perm = 0;
      entry OC_ST_3_T1 && OC_ST_3_perm == 0 / OC_ST_3_perm = 1;
      entry !OC_ST_3_T1 && OC_ST_3_perm == 1 / OC_ST_3_perm = 0;
      entry OC_ST_4_T1 && OC_ST_4_perm == 0 / OC_ST_4_perm = 1;
      entry !OC_ST_4_T1 && OC_ST_4_perm == 1 / OC_ST_4_perm = 0;
      entry OI_LN_0_T1 && OI_LN_0_perm == 0 / OI_LN_0_perm = 1;
      entry !OI_LN_0_T1 && OI_LN_0_perm == 1 / OI_LN_0_perm = 0;
      entry OI_LN_1_T1 && OI_LN_1_perm == 0 / OI_LN_1_perm = 1;
      entry !OI_LN_1_T1 && OI_LN_1_perm == 1 / OI_LN_1_perm = 0;
      entry OI_LN_2_T1 && OI_LN_2_perm == 0 / OI_LN_2_perm = 1;
      entry !OI_LN_2_T1 && OI_LN_2_perm == 1 / OI_LN_2_perm = 0;
    }
    >-> T2;

    state T2 {
      entry IC_JCT_0_T1 && IC_JCT_0_perm == 0 / IC_JCT_0_perm = 2;
      entry !IC_JCT_0_T1 && IC_JCT_0_perm == 2 / IC_JCT_0_perm = 0;
      entry IC_LN_0_T1 && IC_LN_0_perm == 0 / IC_LN_0_perm = 2;
      entry !IC_LN_0_T1 && IC_LN_0_perm == 2 / IC_LN_0_perm = 0;
      entry IC_LN_1_T1 && IC_LN_1_perm == 0 / IC_LN_1_perm = 2;
      entry !IC_LN_1_T1 && IC_LN_1_perm == 2 / IC_LN_1_perm = 0;
      entry IC_LN_2_T1 && IC_LN_2_perm == 0 / IC_LN_2_perm = 2;
      entry !IC_LN_2_T1 && IC_LN_2_perm == 2 / IC_LN_2_perm = 0;
      entry IC_LN_3_T1 && IC_LN_3_perm == 0 / IC_LN_3_perm = 2;
      entry !IC_LN_3_T1 && IC_LN_3_perm == 2 / IC_LN_3_perm = 0;
      entry IC_LN_4_T1 && IC_LN_4_perm == 0 / IC_LN_4_perm = 2;
      entry !IC_LN_4_T1 && IC_LN_4_perm == 2 / IC_LN_4_perm = 0;
      entry IC_LN_5_T1 && IC_LN_5_perm == 0 / IC_LN_5_perm = 2;
      entry !IC_LN_5_T1 && IC_LN_5_perm == 2 / IC_LN_5_perm = 0;
      entry IC_ST_0_T1 && IC_ST_0_perm == 0 / IC_ST_0_perm = 2;
      entry !IC_ST_0_T1 && IC_ST_0_perm == 2 / IC_ST_0_perm = 0;
      entry IC_ST_1_T1 && IC_ST_1_perm == 0 / IC_ST_1_perm = 2;
      entry !IC_ST_1_T1 && IC_ST_1_perm == 2 / IC_ST_1_perm = 0;
      entry IC_ST_2_T1 && IC_ST_2_perm == 0 / IC_ST_2_perm = 2;
      entry !IC_ST_2_T1 && IC_ST_2_perm == 2 / IC_ST_2_perm = 0;
      entry IC_ST_3_T1 && IC_ST_3_perm == 0 / IC_ST_3_perm = 2;
      entry !IC_ST_3_T1 && IC_ST_3_perm == 2 / IC_ST_3_perm = 0;
      entry IC_ST_4_T1 && IC_ST_4_perm == 0 / IC_ST_4_perm = 2;
      entry !IC_ST_4_T1 && IC_ST_4_perm == 2 / IC_ST_4_perm = 0;
      entry IO_LN_0_T1 && IO_LN_0_perm == 0 / IO_LN_0_perm = 2;
      entry !IO_LN_0_T1 && IO_LN_0_perm == 2 / IO_LN_0_perm = 0;
      entry IO_LN_1_T1 && IO_LN_1_perm == 0 / IO_LN_1_perm = 2;
      entry !IO_LN_1_T1 && IO_LN_1_perm == 2 / IO_LN_1_perm = 0;
      entry IO_LN_2_T1 && IO_LN_2_perm == 0 / IO_LN_2_perm = 2;
      entry !IO_LN_2_T1 && IO_LN_2_perm == 2 / IO_LN_2_perm = 0;
      entry KH_LN_0_T1 && KH_LN_0_perm == 0 / KH_LN_0_perm = 2;
      entry !KH_LN_0_T1 && KH_LN_0_perm == 2 / KH_LN_0_perm = 0;
      entry KH_LN_1_T1 && KH_LN_1_perm == 0 / KH_LN_1_perm = 2;
      entry !KH_LN_1_T1 && KH_LN_1_perm == 2 / KH_LN_1_perm = 0;
      entry KH_LN_2_T1 && KH_LN_2_perm == 0 / KH_LN_2_perm = 2;
      entry !KH_LN_2_T1 && KH_LN_2_perm == 2 / KH_LN_2_perm = 0;
      entry KH_LN_3_T1 && KH_LN_3_perm == 0 / KH_LN_3_perm = 2;
      entry !KH_LN_3_T1 && KH_LN_3_perm == 2 / KH_LN_3_perm = 0;
      entry KH_LN_4_T1 && KH_LN_4_perm == 0 / KH_LN_4_perm = 2;
      entry !KH_LN_4_T1 && KH_LN_4_perm == 2 / KH_LN_4_perm = 0;
      entry KH_LN_5_T1 && KH_LN_5_perm == 0 / KH_LN_5_perm = 2;
      entry !KH_LN_5_T1 && KH_LN_5_perm == 2 / KH_LN_5_perm = 0;
      entry KH_LN_6_T1 && KH_LN_6_perm == 0 / KH_LN_6_perm = 2;
      entry !KH_LN_6_T1 && KH_LN_6_perm == 2 / KH_LN_6_perm = 0;
      entry KH_LN_7_T1 && KH_LN_7_perm == 0 / KH_LN_7_perm = 2;
      entry !KH_LN_7_T1 && KH_LN_7_perm == 2 / KH_LN_7_perm = 0;
      entry KH_LN_8_T1 && KH_LN_8_perm == 0 / KH_LN_8_perm = 2;
      entry !KH_LN_8_T1 && KH_LN_8_perm == 2 / KH_LN_8_perm = 0;
      entry KH_ST_0_T1 && KH_ST_0_perm == 0 / KH_ST_0_perm = 2;
      entry !KH_ST_0_T1 && KH_ST_0_perm == 2 / KH_ST_0_perm = 0;
      entry KH_ST_1_T1 && KH_ST_1_perm == 0 / KH_ST_1_perm = 2;
      entry !KH_ST_1_T1 && KH_ST_1_perm == 2 / KH_ST_1_perm = 0;
      entry KH_ST_2_T1 && KH_ST_2_perm == 0 / KH_ST_2_perm = 2;
      entry !KH_ST_2_T1 && KH_ST_2_perm == 2 / KH_ST_2_perm = 0;
      entry KH_ST_3_T1 && KH_ST_3_perm == 0 / KH_ST_3_perm = 2;
      entry !KH_ST_3_T1 && KH_ST_3_perm == 2 / KH_ST_3_perm = 0;
      entry KH_ST_4_T1 && KH_ST_4_perm == 0 / KH_ST_4_perm = 2;
      entry !KH_ST_4_T1 && KH_ST_4_perm == 2 / KH_ST_4_perm = 0;
      entry KH_ST_5_T1 && KH_ST_5_perm == 0 / KH_ST_5_perm = 2;
      entry !KH_ST_5_T1 && KH_ST_5_perm == 2 / KH_ST_5_perm = 0;
      entry KH_ST_6_T1 && KH_ST_6_perm == 0 / KH_ST_6_perm = 2;
      entry !KH_ST_6_T1 && KH_ST_6_perm == 2 / KH_ST_6_perm = 0;
      entry KIO_LN_0_T1 && KIO_LN_0_perm == 0 / KIO_LN_0_perm = 2;
      entry !KIO_LN_0_T1 && KIO_LN_0_perm == 2 / KIO_LN_0_perm = 0;
      entry KIO_LN_1_T1 && KIO_LN_1_perm == 0 / KIO_LN_1_perm = 2;
      entry !KIO_LN_1_T1 && KIO_LN_1_perm == 2 / KIO_LN_1_perm = 0;
      entry OC_JCT_0_T1 && OC_JCT_0_perm == 0 / OC_JCT_0_perm = 2;
      entry !OC_JCT_0_T1 && OC_JCT_0_perm == 2 / OC_JCT_0_perm = 0;
      entry OC_LN_0_T1 && OC_LN_0_perm == 0 / OC_LN_0_perm = 2;
      entry !OC_LN_0_T1 && OC_LN_0_perm == 2 / OC_LN_0_perm = 0;
      entry OC_LN_1_T1 && OC_LN_1_perm == 0 / OC_LN_1_perm = 2;
      entry !OC_LN_1_T1 && OC_LN_1_perm == 2 / OC_LN_1_perm = 0;
      entry OC_LN_2_T1 && OC_LN_2_perm == 0 / OC_LN_2_perm = 2;
      entry !OC_LN_2_T1 && OC_LN_2_perm == 2 / OC_LN_2_perm = 0;
      entry OC_LN_3_T1 && OC_LN_3_perm == 0 / OC_LN_3_perm = 2;
      entry !OC_LN_3_T1 && OC_LN_3_perm == 2 / OC_LN_3_perm = 0;
      entry OC_LN_4_T1 && OC_LN_4_perm == 0 / OC_LN_4_perm = 2;
      entry !OC_LN_4_T1 && OC_LN_4_perm == 2 / OC_LN_4_perm = 0;
      entry OC_LN_5_T1 && OC_LN_5_perm == 0 / OC_LN_5_perm = 2;
      entry !OC_LN_5_T1 && OC_LN_5_perm == 2 / OC_LN_5_perm = 0;
      entry OC_ST_0_T1 && OC_ST_0_perm == 0 / OC_ST_0_perm = 2;
      entry !OC_ST_0_T1 && OC_ST_0_perm == 2 / OC_ST_0_perm = 0;
      entry OC_ST_1_T1 && OC_ST_1_perm == 0 / OC_ST_1_perm = 2;
      entry !OC_ST_1_T1 && OC_ST_1_perm == 2 / OC_ST_1_perm = 0;
      entry OC_ST_2_T1 && OC_ST_2_perm == 0 / OC_ST_2_perm = 2;
      entry !OC_ST_2_T1 && OC_ST_2_perm == 2 / OC_ST_2_perm = 0;
      entry OC_ST_3_T1 && OC_ST_3_perm == 0 / OC_ST_3_perm = 2;
      entry !OC_ST_3_T1 && OC_ST_3_perm == 2 / OC_ST_3_perm = 0;
      entry OC_ST_4_T1 && OC_ST_4_perm == 0 / OC_ST_4_perm = 2;
      entry !OC_ST_4_T1 && OC_ST_4_perm == 2 / OC_ST_4_perm = 0;
      entry OI_LN_0_T1 && OI_LN_0_perm == 0 / OI_LN_0_perm = 2;
      entry !OI_LN_0_T1 && OI_LN_0_perm == 2 / OI_LN_0_perm = 0;
      entry OI_LN_1_T1 && OI_LN_1_perm == 0 / OI_LN_1_perm = 2;
      entry !OI_LN_1_T1 && OI_LN_1_perm == 2 / OI_LN_1_perm = 0;
      entry OI_LN_2_T1 && OI_LN_2_perm == 0 / OI_LN_2_perm = 2;
      entry !OI_LN_2_T1 && OI_LN_2_perm == 2 / OI_LN_2_perm = 0;
    }
    >-> tick;

    region trains:

    initial state IC_ST_2 {

      initial state entering {
        entry / IC_ST_4_T1 = true;
        entry / IC_LN_0_T1 = true;
      }
      --> leaving with 'contact[IC_LN_0][1]' && IC_ST_4_perm == 1 &&
      IC_LN_0_perm == 1
      --> waiting with 'contact[IC_LN_0][1]';

      state waiting {
        entry / 'setsignal(railway, IC_ST_2, 1, RED)';
        entry / 'settrack(railway, IC_ST_2, BRAKE, 0)';
      }
      --> leaving with IC_ST_4_perm == 1 && IC_LN_0_perm == 1;

      state leaving {
        entry / 'setpoint(railway, 23, BRANCH)';
        entry / 'setpoint(railway, 24, BRANCH)';
        entry / 'setpoint(railway, 29, STRAIGHT)';
        entry / 'setsignal(railway, IC_ST_2, 1, GREEN)';
        entry / 'settrack(railway, IC_ST_2, FWD, 100)';
        entry / 'settrack(railway, IC_ST_4, FWD, 100)';
        entry / 'setsignal(railway, IC_LN_0, 1, YELLOW)';
        entry / 'settrack(railway, IC_LN_0, FWD, 100)';
      }
      --> f;

      final state f;
    }
    --> IC_LN_0 with 'contact[IC_LN_0][0]';

    state IC_LN_0 {

      initial state entering {
        entry / 'setsignal(railway, IC_ST_2, 1, RED)';
        entry / 'settrack(railway, IC_ST_2, OFF, 0)';
        entry / IC_ST_2_T1 = false;
        entry / IC_LN_1_T1 = true;
      }
      --> leaving with 'contact[IC_LN_0][1]' && IC_LN_1_perm == 1
      --> waiting with 'contact[IC_LN_0][1]';

      state waiting {
        entry / 'setsignal(railway, IC_LN_0, 1, RED)';
        entry / 'settrack(railway, IC_LN_0, BRAKE, 0)';
        exit / 'setsignal(railway, IC_LN_0, 1, GREEN)';
        exit / 'settrack(railway, IC_LN_0, FWD, 100)';
      }
      --> leaving with IC_LN_1_perm == 1;

      state leaving {
        entry / 'setsignal(railway, IC_LN_0, 1, GREEN)';
        entry / 'setsignal(railway, IC_LN_1, 1, YELLOW)';
        entry / 'settrack(railway, IC_LN_1, FWD, 100)';
      }
      --> f;

      final state f;

      region cleanup:

      initial state entering
      --> done with 'contact[IC_LN_0][0]' /
      'settrack(railway, IC_ST_4, OFF, 0)'; IC_ST_4_T1 = false;

      final state done;
    }
    >-> x1;

    state x1
    --> IC_LN_1 with 'contact[IC_LN_1][0]';

    state IC_LN_1 {

      initial state entering {
        entry / IC_LN_2_T1 = true;
      }
      --> leaving with 'contact[IC_LN_1][1]' && IC_LN_2_perm == 1
      --> waiting with 'contact[IC_LN_1][1]';

      state waiting {
        entry / 'setsignal(railway, IC_LN_1, 1, RED)';
        entry / 'settrack(railway, IC_LN_1, BRAKE, 0)';
        exit / 'setsignal(railway, IC_LN_1, 1, GREEN)';
        exit / 'settrack(railway, IC_LN_1, FWD, 100)';
      }
      --> leaving with IC_LN_2_perm == 1;

      state leaving {
        entry / 'setsignal(railway, IC_LN_1, 1, GREEN)';
        entry / 'setsignal(railway, IC_LN_2, 1, YELLOW)';
        entry / 'settrack(railway, IC_LN_2, FWD, 100)';
      }
      --> f;

      final state f;

      region cleanup:

      initial state entering
      --> done with 'contact[IC_LN_1][0]' /
      'setsignal(railway, IC_LN_0, 1, RED)';
      'settrack(railway, IC_LN_0, OFF, 0)'; IC_LN_0_T1 = false;

      final state done;
    }
    >-> x2;

    state x2
    --> IC_LN_2 with 'contact[IC_LN_2][0]';

    state IC_LN_2 {

      initial state entering {
        entry / IC_LN_3_T1 = true;
      }
      --> leaving with 'contact[IC_LN_2][1]' && IC_LN_3_perm == 1
      --> waiting with 'contact[IC_LN_2][1]';

      state waiting {
        entry / 'setsignal(railway, IC_LN_2, 1, RED)';
        entry / 'settrack(railway, IC_LN_2, BRAKE, 0)';
        exit / 'setsignal(railway, IC_LN_2, 1, GREEN)';
        exit / 'settrack(railway, IC_LN_2, FWD, 100)';
      }
      --> leaving with IC_LN_3_perm == 1;

      state leaving {
        entry / 'setsignal(railway, IC_LN_2, 1, GREEN)';
        entry / 'setsignal(railway, IC_LN_3, 1, YELLOW)';
        entry / 'settrack(railway, IC_LN_3, FWD, 100)';
      }
      --> f;

      final state f;

      region cleanup:

      initial state entering
      --> done with 'contact[IC_LN_2][0]' /
      'setsignal(railway, IC_LN_1, 1, RED)';
      'settrack(railway, IC_LN_1, OFF, 0)'; IC_LN_1_T1 = false;

      final state done;
    }
    >-> x3;

    state x3
    --> IC_LN_3 with 'contact[IC_LN_3][0]';

    state IC_LN_3 {

      initial state entering {
        entry / IC_LN_4_T1 = true;
      }
      --> leaving with 'contact[IC_LN_3][1]' && IC_LN_4_perm == 1
      --> waiting with 'contact[IC_LN_3][1]';

      state waiting {
        entry / 'setsignal(railway, IC_LN_3, 1, RED)';
        entry / 'settrack(railway, IC_LN_3, BRAKE, 0)';
        exit / 'setsignal(railway, IC_LN_3, 1, GREEN)';
        exit / 'settrack(railway, IC_LN_3, FWD, 100)';
      }
      --> leaving with IC_LN_4_perm == 1;

      state leaving {
        entry / 'setsignal(railway, IC_LN_3, 1, GREEN)';
        entry / 'setsignal(railway, IC_LN_4, 1, YELLOW)';
        entry / 'settrack(railway, IC_LN_4, FWD, 100)';
      }
      --> f;

      final state f;

      region cleanup:

      initial state entering
      --> done with 'contact[IC_LN_3][0]' /
      'setsignal(railway, IC_LN_2, 1, RED)';
      'settrack(railway, IC_LN_2, OFF, 0)'; IC_LN_2_T1 = false;

      final state done;
    }
    >-> x4;

    state x4
    --> IC_LN_4 with 'contact[IC_LN_4][0]';

    state IC_LN_4 {

      initial state entering {
        entry / IC_JCT_0_T1 = true;
        entry / IC_LN_5_T1 = true;
      }
      --> leaving with 'contact[IC_LN_4][1]' && IC_JCT_0_perm == 1 &&
      IC_LN_5_perm == 1
      --> waiting with 'contact[IC_LN_4][1]';

      state waiting {
        entry / 'setsignal(railway, IC_LN_4, 1, RED)';
        entry / 'settrack(railway, IC_LN_4, BRAKE, 0)';
        exit / 'setsignal(railway, IC_LN_4, 1, GREEN)';
        exit / 'settrack(railway, IC_LN_4, FWD, 100)';
      }
      --> leaving with IC_JCT_0_perm == 1 && IC_LN_5_perm == 1;

      state leaving {
        entry / 'setpoint(railway, 13, STRAIGHT)';
        entry / 'setpoint(railway, 11, STRAIGHT)';
        entry / 'settrack(railway, IC_JCT_0, FWD, 100)';
        entry / 'setsignal(railway, IC_LN_5, 1, YELLOW)';
        entry / 'settrack(railway, IC_LN_5, FWD, 100)';
      }
      --> f;

      final state f;

      region cleanup:

      initial state entering
      --> done with 'contact[IC_LN_4][0]' /
      'setsignal(railway, IC_LN_3, 1, RED)';
      'settrack(railway, IC_LN_3, OFF, 0)'; IC_LN_3_T1 = false;

      final state done;
    }
    >-> x5;

    state x5
    --> IC_LN_5 with 'contact[IC_LN_5][0]';

    state IC_LN_5 {

      initial state entering {
        entry / 'setsignal(railway, IC_LN_4, 1, RED)';
        entry / 'settrack(railway, IC_LN_4, OFF, 0)';
        entry / IC_LN_4_T1 = false;
        entry / IC_ST_0_T1 = true;
        entry / IC_ST_2_T1 = true;
      }
      --> leaving with 'contact[IC_LN_5][1]' && IC_ST_0_perm == 1 &&
      IC_ST_2_perm == 1
      --> waiting with 'contact[IC_LN_5][1]';

      state waiting {
        entry / 'setsignal(railway, IC_LN_5, 1, RED)';
        entry / 'settrack(railway, IC_LN_5, BRAKE, 0)';
        exit / 'setsignal(railway, IC_LN_5, 1, GREEN)';
        exit / 'settrack(railway, IC_LN_5, FWD, 100)';
      }
      --> leaving with IC_ST_0_perm == 1 && IC_ST_2_perm == 1;

      state leaving {
        entry / 'setpoint(railway, 18, STRAIGHT)';
        entry / 'setpoint(railway, 20, BRANCH)';
        entry / 'setpoint(railway, 19, BRANCH)';
        entry / 'settrack(railway, IC_ST_0, FWD, 100)';
        entry / 'setsignal(railway, IC_ST_2, 1, YELLOW)';
        entry / 'settrack(railway, IC_ST_2, FWD, 100)';
      }
      --> f;

      final state f;

      region cleanup:

      initial state entering
      --> done with 'contact[IC_LN_5][0]' /
      'settrack(railway, IC_JCT_0, OFF, 0)'; IC_JCT_0_T1 = false;

      final state done;
    }
    >-> x6;

    state x6
    --> preIC_ST_2 with 'contact[IC_ST_2][0]';

    state preIC_ST_2 {

      initial state entering {
        entry / 'setsignal(railway, IC_ST_2, 1, RED)';
      }
      --> stopping with 'contact[IC_ST_2][1]';

      state stopping {
        entry / 'settrack(railway, IC_ST_2, BRAKE, 0)';
      }
      --> f;

      final state f;

      region cleanup:

      initial state entering
      --> done with 'contact[IC_ST_2][0]' /
      'setsignal(railway, IC_LN_5, 1, RED)';
      'settrack(railway, IC_LN_5, OFF, 0)'; IC_LN_5_T1 = false;
      'settrack(railway, IC_ST_0, OFF, 0)'; IC_ST_0_T1 = false;

      final state done;
    }
    >-> waiting;

    state waiting {

      initial state c0
      --> c1 with second;

      state c1
      --> c2 with second;

      state c2
      --> c3 with second;

      state c3
      --> c4 with second;

      state c4
      --> c5 with second;

      state c5
      --> c6 with second;

      state c6
      --> c7 with second;

      state c7
      --> c8 with second;

      state c8
      --> c9 with second;

      state c9
      --> done with second;

      final state done;
    }
    >-> IC_ST_2;
  };
}